Firmware/Software Tech Lead (AI Infrastructure)

Location: San Jose, California, United States

Salary: $160,000–$200,000 per year, depending on experience, level, and business need. Additional discretionary bonus, incentives, and benefits may apply.

Company

hirify.global provides rack-scale AI infrastructure through connectivity solutions based on CXL, Ethernet, NVLink, PCIe, UALink, and its COSMOS software suite.

What you will do

• Own RTL design for assigned connectivity blocks from microarchitecture through synthesis sign-off.
• Develop synthesizable Verilog/SystemVerilog with strong attention to power, performance, and area.
• Translate specifications into implementation-ready microarchitecture with architecture partners.
• Drive design reviews, lint, CDC, timing closure, and silicon-readiness activities.
• Collaborate with verification, DFT, and physical design teams on test plans, coverage, scan, BIST, floorplanning, and timing closure.
• Mentor junior engineers, improve design methodology, and debug pre-silicon and post-silicon issues across RTL, gate-level, and emulation environments.

Requirements

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related field.
• 5+ years of digital design experience, including at least one complete chip delivered from specification to tapeout.
• Strong proficiency in Verilog/SystemVerilog, RTL coding, and synthesis flows.
• Hands-on experience with timing closure, CDC, lint, and low-power design techniques.
• Understanding of high-speed serial interfaces such as PCIe or Ethernet and SoC integration.

Nice to have

• MS or PhD in Electrical Engineering or Computer Engineering.
• Experience with PCIe Gen5/Gen6, CXL, UALink, UCIe, or Ethernet MAC/PCS designs.
• Familiarity with formal verification, emulation, or assertion-based methodologies.
• Experience with advanced process nodes such as 7nm, 5nm, or below.
• Strong debugging skills across pre-silicon and post-silicon environments.

Culture & Benefits

• Work on connectivity silicon for large-scale AI infrastructure.
• Collaborate with hyperscalers and ecosystem partners on emerging rack-scale interconnect technologies.
• Contribute to design methodology, scripts, and engineering best practices at a hyper-growth company.
• Discretionary bonus, incentives, and benefits may be available.
• Applications are encouraged from people with diverse backgrounds and experiences.