обновлено 1 день назад
Lead ASIC Design Engineer (Digital Design)
143 800 - 230 000$
Мэтч & Сопровод
Для мэтча с этой вакансией нужен Plus
Описание вакансии
Текст:
TL;DR
Lead ASIC Design Engineer (Digital Design): Leading next-generation silicon projects with an accent on top-level architecture, microarchitecture, and full chip integration. Focus on driving the design outcome from product definition to tape-out sign-off and managing PPA targets.
Location: San Jose, California. Must have legal authorization to work in the US
Salary: $143,800 - $230,000
Company
is a global leader in semiconductor and infrastructure software solutions.
What you will do
- Serve as the Chip Lead, defining top-level digital architecture and owning the integration lifecycle.
- Coordinate between Logic Design, Physical Design, and Verification to meet PPA targets.
- Author and optimize synthesizable SystemVerilog/Verilog RTL for complex digital blocks.
- Drive chip timing constraints (SDC), CDC strategies, and block-level timing budgets.
- Manage logic synthesis and Static Timing Analysis (STA) using EDA tools.
- Collaborate with post-silicon validation teams for chip bring-up and debug.
Requirements
- Bachelor’s or Master’s degree in Electrical or Computer Engineering.
- 12+ years of industry experience in ASIC/SoC digital design.
- Proven track record of owning chip projects or serving as a design lead.
- Expert proficiency in SystemVerilog/Verilog and microarchitecture principles.
- Deep experience with Synopsys or Cadence EDA tools for synthesis and STA.
- Legal authorization to work in the US is required
Nice to have
- Experience with SerDes, PCIe, DDR, or high-speed PHY-adjacent architectures.
- Familiarity with DFT planning, scan insertion, and ATPG.
- Scripting skills in Python, Tcl, or Perl for design flow automation.
Culture & Benefits
- Competitive annual base salary with discretionary annual bonuses.
- New hire equity grants and annual equity awards.
- Comprehensive medical, dental, and vision plans.
- 401(k) plan with company matching.
- Employee Stock Purchase Program (ESPP).
- Paid holidays, sick leave, and vacation time.
Будьте осторожны: если работодатель просит войти в их систему, используя iCloud/Google, прислать код/пароль, запустить код/ПО, не делайте этого - это мошенники. Обязательно жмите "Пожаловаться" или пишите в поддержку. Подробнее в гайде →
Похожие вакансии
6 дней назад
Senior Staff Digital Design Engineer (ASIC)
135 900 - 201 130$
5 дней назад
ASIC Physical Design Engineer (SoC)
148 900 - 276 500$
1 день назад
Lead Functional Product Engineer (Power Analysis)
114 800 - 213 200$
5 дней назад
Analog Circuit Design Engineer (VLSI)
122 440 - 232 190$
5 дней назад
Senior Principal Engineer (Hardware Chip Lead)
182 360 - 273 200$
4 дня назад
Principal Physical Design/Implementation Engineer (Semiconductor)
154 680 - 231 700$