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Lead ASIC Design Engineer (Digital Design)

143 800 - 230 000$
Формат работы
onsite
Тип работы
fulltime
Грейд
senior/lead
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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TL;DR
Lead ASIC Design Engineer (Digital Design): Leading next-generation silicon projects from top-level architecture and microarchitecture through chip integration and foundry tape-out with an accent on SystemVerilog/Verilog RTL, timing constraints, CDC strategy, and front-end EDA flows. Focus on driving PPA targets, coordinating analog, physical design, and verification teams, and delivering first-pass silicon through post-silicon bring-up and debug.

Location: San Jose, California, USA; must have legal authorization to work in the US

Annual base salary: $143,800–$230,000

Company

hirify.global develops semiconductor and silicon solutions, including next-generation ASIC and SoC projects.

What you will do

  • Serve as Chip Lead and own top-level digital architecture, microarchitecture, IP partitioning, and full-chip integration.
  • Coordinate logic design, physical design, architecture, analog design, and design verification teams to meet power, performance, and area targets.
  • Drive RTL development, synthesis, static timing analysis, linting, CDC analysis, and top-level timing constraint ownership.
  • Manage analog macros, mixed-signal blocks, and third-party soft and hard IP integration.
  • Own tape-out sign-off and collaborate with post-silicon validation and software teams during chip bring-up and lab debug.
  • Mentor mid-level and junior engineers through technical guidance, code reviews, and architectural design work.

Requirements

  • Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
  • 12+ years of direct ASIC/SoC digital design experience, including ownership of chip projects or design leadership.
  • Expert-level SystemVerilog/Verilog proficiency and strong digital microarchitecture skills.
  • Deep experience with synthesis, STA, CDC analysis, and Synopsys or Cadence front-end EDA tools.
  • Proven history of successful first-pass silicon tape-outs on modern process technologies.
  • Legal authorization to work in the US is required.

Nice to have

  • Experience with mixed-signal or high-speed PHY-adjacent architectures such as SerDes, PCIe, DDR, or custom interconnects.
  • DFT planning experience, including scan insertion, ATPG, and boundary scan.
  • Scripting experience with Python, Tcl, or Perl.

Culture & Benefits

  • Full-time employment with medical, dental, and vision coverage.
  • 401(k) participation with company matching and an Employee Stock Purchase Program.
  • Discretionary annual bonus, new-hire equity grant, and annual equity awards.
  • Paid holidays, sick leave, vacation time, and applicable family and other leaves of absence.
  • Employee Assistance Program.

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