ASIC Design Engineer

Location: Onsite, primarily working from an HPE office

Company

A global edge-to-cloud technology company developing solutions that connect, protect, analyze, and process data and applications.

What you will do

• Define and architect high-performance blocks for advanced networking ASICs.
• Develop micro-architecture and Verilog RTL logic designs optimized for throughput and power efficiency.
• Collaborate with verification engineers on test plans and debug test failures.
• Work with physical design engineers on timing constraints, timing violation analysis, and timing fixes.
• Analyze and evaluate VLSI designs for prototype and production solutions.

Requirements

• BSEE or MSEE with 5+ years of experience in ASIC or VLSI design.
• Strong Verilog RTL coding and ASIC debugging skills.
• Knowledge of high-performance memory subsystems.
• Knowledge of multi-domain clock synchronization and high-speed serial interfaces.
• Strong problem-solving, written, and verbal communication skills.

Nice to have

• Experience with Synopsys Design Compiler, Verplex LEC, and SpyGlass.
• Experience designing ASICs for networking protocols such as Ethernet and FCoE.

Culture & Benefits

• Comprehensive health, financial, and emotional wellbeing benefits.
• Personal and professional development programs supporting career growth and mobility.
• Inclusive work environment that values varied backgrounds and individual uniqueness.
• Flexibility to manage work and personal needs within the onsite work arrangement.