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7 часов назад

Staff DFT Design Engineer (AI)

Тип работы

fulltime

Грейд

senior

Английский

Страна

Malaysia

Вакансия из Hirify Global, списка международных tech-компаний
Для мэтча и отклика нужен Plus

Мэтч & Сопровод

Для мэтча с этой вакансией нужен Plus

Описание вакансии

Текст:

TL;DR

Staff DFT Design Engineer (FPGA/SoC and AI): Defining DFT architecture and implementing scan, ATPG, memory BIST, IJTAG, and functional-safety solutions for complex FPGA and SoC designs with an accent on sign-off quality, timing, power, and manufacturing yield. Focus on resolving testability and clocking challenges, improving post-silicon coverage and test cost, and guiding DFT engineers across design, validation, and manufacturing teams.

Location: Penang 15, Penang, Malaysia

Company

hirify.global is hiring for a semiconductor design engineering role focused on design-for-test implementation and leadership.

What you will do

Define end-to-end DFT architecture, strategy, methodology, scalability, reuse, and roadmap alignment for complex FPGA and SoC designs.
Lead scan architecture, scan insertion, ATPG generation, coverage analysis, cell-aware and power-aware testing, memory BIST and repair, SSN, ICL extraction, and PDL retargeting.
Drive DFT sign-off using SpyGlassDFT or equivalent tools and resolve testability, clocking, reset, timing, congestion, and power challenges.
Collaborate with front-end, physical design, post-silicon, test engineering, ATE, validation, manufacturing, and program management teams.
Improve silicon learning, yield, test coverage, test-hole reduction, and test-cost optimization.
Mentor DFT engineers, set technical standards, review implementations, and provide expertise on complex testability issues.

Requirements

Bachelor’s or Master’s degree in Electrical, Electronic Engineering, or a related field.
10+ years of industry experience in DFT design with significant hands-on ownership.
Strong experience with DFT methodology, architecture, custom design blocks, and PNR flows.
Strong Verilog and/or SystemVerilog proficiency.
Knowledge of IEEE 1149.1 JTAG and/or IEEE 1687 IJTAG, plus experience with timing constraints across multiple clock domains.
Proven ability to collaborate across architecture, RTL, physical design, test, manufacturing, and multi-site teams, including driving AI or LLM solutions to improve DFT implementations.

Nice to have

Experience with post-silicon debug, yield ramp, production issues, industrial ATE platforms, and tester limitations.
DFT design verification, flow development, infrastructure improvement, low-power DFT, and test-power management experience.
Scripting and automation skills with Python, Tcl, or Perl.

Culture & Benefits

Regular full-time employment.
Shift 1 aligned with Malaysia.
Cross-functional collaboration across design, validation, manufacturing, and program management.

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