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обновлено 11 дней назад

Staff SOC DFT Engineer

Формат работы
hybrid
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
Malaysia
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

Текст:
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TL;DR
Staff SOC DFT Engineer (DFT/DFD, RTL): Developing and integrating advanced design-for-test methodologies and features for complex SoC designs with an accent on test coverage, post-silicon efficiency, and design verification. Focus on debugging and validating DFT features, optimizing workflows with AI, and collaborating across design, verification, and manufacturing teams.

Location: Hybrid work model in Penang, Malaysia, with time split between the assigned hirify.global site and off-site work.

Company

hirify.global develops processors, semiconductor solutions, memory and programmable technologies, and connectivity products for business and consumer applications.

What you will do

  • Develop and implement advanced DFT methodologies for complex SoC designs to maximize test coverage and efficiency.
  • Define and optimize post-silicon strategies and requirements with design, verification, and manufacturing teams.
  • Integrate DFT/DFD features into RTL and verify design-for-testability requirements.
  • Debug and validate DFT features in collaboration with post-silicon teams.
  • Track emerging DFT/DFD technologies and apply AI to improve workflows and post-silicon efficiency.

Requirements

  • Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related field.
  • 5+ years of experience in DFT, SoC design, or related semiconductor design areas.
  • Expertise in RTL design using Verilog, VHDL, or SystemVerilog.
  • Experience working with cross-functional teams involved in design, verification, manufacturing, and post-silicon validation.

Nice to have

  • Familiarity with AI applications, advanced low-power or high-performance SoC DFT methods, and Python or other scripting languages.
  • Knowledge of IEEE 1687 (IJTAG), IEEE 1149.1 (JTAG), or IEEE 1500 standards.
  • Experience with Synopsys DFT Compiler, Mentor Tessent, or Cadence Modus.
  • Experience managing multifunctional teams or complex SoC projects.

Culture & Benefits

  • Hybrid work model combining on-site and off-site work.
  • Collaborative environment involving design, verification, manufacturing, and post-silicon teams.
  • Full-time experienced-hire position on Shift 1 in Malaysia.
  • Employment practices follow hirify.global’s equal-opportunity and responsible-business commitments.

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