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7 часов назад

DFT Implementation Engineer (Semiconductor)

141 910 - 200 340$
Формат работы
onsite
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify RU Global, списка компаний с восточно-европейскими корнями
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Описание вакансии

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TL;DR

DFT Implementation Engineer (Semiconductor): Designing and integrating Design for Test (DFT) capabilities into cutting-edge SoC and IP solutions with an accent on test coverage and silicon efficiency. Focus on RTL coding for SCAN, MBIST, and BSCAN, as well as optimizing power, performance, and area for high-volume manufacturing.

Location: On-site in Austin, Texas, US

Salary: $141,910–$200,340 USD

Company

hirify.global is a global leader in the design and manufacturing of semiconductor chips and silicon solutions.

What you will do

  • Develop logic design and RTL coding to support DFT features such as SCAN, MBIST, and BSCAN.
  • Collaborate in defining architecture and microarchitecture features for blocks, subsystems, and SoCs.
  • Optimize designs to meet power, performance, area, and test coverage goals while adhering to design integrity standards.
  • Write, integrate, and verify RTL and structural code for DFT functionality.
  • Develop high-volume manufacturing (HVM) content for rapid bring-up and production on automatic test equipment (ATE).
  • Collaborate with post-silicon and manufacturing teams to verify features on silicon and document learnings.

Requirements

  • Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field.
  • 5+ years of experience in DFT, SoC design, or related semiconductor design areas.
  • Experience with Tessent Shell flows and SSN methodology.
  • Hands-on experience with ATPG, scan insertion, and/or MBIST/repair.
  • RTL design experience using hardware description languages such as Verilog, VHDL, or SystemVerilog.

Nice to have

  • Experience with Tessent Fast IO, ISTK, and IEEE standards (1687, 1149.1, 1500, 1838).
  • Proficiency in scripting languages such as TCL, Perl, or Python for design automation.
  • Knowledge of timing constraints, UPF, and low-power design and test methodologies.
  • Exposure to large ASIC applications in design or test.

Culture & Benefits

  • Competitive pay and stock bonuses.
  • Comprehensive benefit programs including health insurance, retirement, and vacation.
  • Opportunity to work on industry-leading SoC and IP solutions in a highly innovative environment.

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