8 часов назад
DFX Design Architect
Мэтч & Сопровод
Для мэтча с этой вакансией нужен Plus
Описание вакансии
Текст:
TL;DR
DFX Design Architect (DFT/DFD, FPGA and SoC): Defining DFX architectures for next-generation multi-die FPGA and SoC families with an accent on test-cost optimization, advanced DFT standards, and on-chip debug infrastructure. Focus on architecting chiplet and high-speed transceiver testing, reducing test data volume and application time, and solving complex silicon bring-up and failure-analysis challenges.
Location: Penang 15, Penang, Malaysia. Onsite role on Shift 1 (Malaysia).
Company
develops next-generation FPGA and SoC semiconductor products.
What you will do
- Define and document DFX architectures for multi-die chiplet systems, high-speed transceivers, and large FPGA fabrics.
- Drive adoption of IEEE 1687 (IJTAG), IEEE 1838 (3D-IC), High-Speed Link Testing, and other advanced DFX features.
- Develop test-cost optimization strategies using test-data compression and adaptive testing to reduce test data volume and application time.
- Lead on-chip debug architecture, including logic analyzers, trace buffers, and scan-dump infrastructure.
- Collaborate with silicon architecture, physical design, manufacturing, and post-silicon system-debug teams to integrate DFT and DFD requirements into hardware specifications.
- Influence EDA vendor roadmaps and mentor senior and staff engineers at the Penang site.
Requirements
- BS, MS, or PhD in Electrical, Electronics, Computer Engineering, or a related field.
- 10–12 years of hands-on DFT/DFD experience, including at least 4 years in an architecture or lead role.
- Deep expertise in hierarchical DFT, Logic/Memory BIST, scan compression, boundary scan, JTAG/iJTAG, and established DFT standards.
- Experience with ASIC and FPGA product life cycles, 2.5D/3D packaging, interposers, TSVs, silicon bring-up, and failure analysis.
- Expertise with Tessent, DesignCompiler/DFTMAX, or equivalent EDA suites, plus scripting in Tcl or Python.
- Experience designing DFX architectures for ASIL-D and other industrial functional-safety requirements.
Nice to have
- Understanding of FPGA-specific testing, including configuration RAM testing and programmable interconnect verification.
Culture & Benefits
- High-visibility technical leadership role with collaboration across global engineering and manufacturing sites.
- Opportunity to present technical roadmaps to executive leadership and global stakeholders.
- Regular employment position based at the Penang engineering site.
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