Principal Engineer – Design (ASIC)

Location: Penang, Malaysia

Company

hirify.global develops semiconductor products and technologies used in systems worldwide.

What you will do

• Lead ASIC design implementation from architectural and micro-architectural understanding through timing signoff and tapeout.
• Develop and sign off RTL-to-GDS implementation projects and improve design implementation flows.
• Define, review, and validate timing constraints with designers and architects.
• Implement DFT capabilities including scan insertion, compression, LOC/LOS, and RAMBIST.
• Optimize designs for low power through architectural feedback, synthesis, layout, and leakage or dynamic power control techniques.
• Provide technical guidance, document implementation procedures, and drive improved design methodologies.

Requirements

• Bachelor’s or Master’s degree in Electrical or Electronics Engineering.
• 12–16 years of ASIC IC design experience.
• Expertise with Cadence Genus or Synopsys DesignCompiler.
• Expertise with Cadence Tempus or Synopsys PrimeTime.
• Strong problem-solving and critical-thinking skills, including the ability to guide team members through complex challenges.
• Ability to work with project managers, product-development and ATPG teams, and CAD/technical-assistance teams.

Nice to have

• Experience with 7 nm and smaller advanced process nodes.
• Familiarity with SystemVerilog foundations and coding.
• Strong scripting skills in Perl, Tcl, Shell, or Python.
• Experience creating technical intellectual property such as patents and trade secrets.

Culture & Benefits

• Full-time position within a global semiconductor organization.
• Culture focused on trust, empowerment, respect, diversity, communication, and employee development.
• Access to leadership and career-development programs.
• Travel requirement of 0%–25%.