Principal Engineer – Design (ASIC)

Location: Penang, Malaysia

Company

hirify.global is a global technology company developing semiconductor products and solutions.

What you will do

• Lead ASIC design implementation from architectural and micro-architectural understanding through RTL-to-GDS implementation and timing signoff for tapeout.
• Develop and sign off IC design projects while improving implementation flows and methodologies.
• Derive, review, and validate timing constraints with designers and architects.
• Implement DFT features including scan insertion, compression, LOC/LOS, and RAMBIST while balancing performance, schedule, and coverage.
• Drive low-power design through architectural feedback, synthesis and layout optimization, and leakage and dynamic power control.
• Provide technical guidance, document implementation decisions, manage design-control audits and tickets, and collaborate with project, product-development, ATPG, CAD, and technical-assistance teams.

Requirements

• Bachelor’s or Master’s degree in Electrical or Electronics Engineering.
• 12–16 years of ASIC IC design experience.
• Expertise with Cadence Genus or Synopsys Design Compiler.
• Expertise with Cadence Tempus or Synopsys PrimeTime.
• Strong problem-solving, critical-thinking, and technical leadership skills.

Nice to have

• Experience with 7nm and below advanced process nodes.
• Familiarity with SystemVerilog foundations and coding.
• Scripting skills in Perl, Tcl, Shell, or Python.

Culture & Benefits

• Full-time position within a large global technology organization.
• Culture focused on trust, empowerment, respect, diversity, communication, employee development, and stability.
• Access to leadership and career-development programs.
• Travel requirement of 0%–25%.