ΠΎΠ±Π½ΠΎΠ²Π»Π΅Π½ΠΎ 1 ΠΌΠ΅ΡΡΡ Π½Π°Π·Π°Π΄
CPU Design Verification Engineer (SystemVerilog/UVM)
ΠΡΡΡ & Π‘ΠΎΠΏΡΠΎΠ²ΠΎΠ΄
ΠΠ»Ρ ΠΌΡΡΡΠ° Ρ ΡΡΠΎΠΉ Π²Π°ΠΊΠ°Π½ΡΠΈΠ΅ΠΉ Π½ΡΠΆΠ΅Π½ Plus
ΠΠΏΠΈΡΠ°Π½ΠΈΠ΅ Π²Π°ΠΊΠ°Π½ΡΠΈΠΈ
Π’Π΅ΠΊΡΡ:
TL;DR
CPU Design Verification Engineer (SystemVerilog/UVM): Performing pre-silicon functional verification of CPU logic by developing verification plans, test benches, simulation models, and coverage-driven environments with an accent on CPU microarchitecture, functional correctness, and performance and power goals. Focus on reproducing and debugging failing tests, identifying root causes, implementing corrective measures, and collaborating with CPU architects and RTL developers.
Location: On-site in Penang, Malaysia
Company
's Silicon and Platform Engineering Group delivers silicon and platform solutions and defines next-generation computing experiences.
What you will do
- Perform pre-silicon functional verification of CPU logic against specification requirements.
- Develop IP verification plans, test benches, simulation models, and verification environments for CPU microarchitecture coverage.
- Execute verification plans, run system simulations, and uncover design bugs.
- Replicate, debug, and root-cause issues in the pre-silicon environment, then implement corrective measures.
- Collaborate with CPU architects and RTL developers to verify complex architectural and microarchitectural features and meet functional, performance, and power goals.
- Document verification plans, lead technical reviews, and improve functional verification infrastructure and methodologies.
Requirements
- Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related field.
- Good knowledge of CPU architecture and computer systems.
- Experience with SystemVerilog and UVM.
- Experience with scripting in Perl or Python and with C++ programming.
- Familiarity with verification tools and methodologies.
- Strong problem-solving, debugging, communication, and collaboration skills.
Culture & Benefits
- Full-time experienced-hire position.
- Shift 1 schedule aligned with Malaysia.
- On-site work model.
- Dynamic, fast-paced engineering environment.
- Employment practices follow local equal-opportunity and ethical hiring requirements.
ΠΡΠ΄ΡΡΠ΅ ΠΎΡΡΠΎΡΠΎΠΆΠ½Ρ: Π΅ΡΠ»ΠΈ ΡΠ°Π±ΠΎΡΠΎΠ΄Π°ΡΠ΅Π»Ρ ΠΏΡΠΎΡΠΈΡ Π²ΠΎΠΉΡΠΈ Π² ΠΈΡ ΡΠΈΡΡΠ΅ΠΌΡ, ΠΈΡΠΏΠΎΠ»ΡΠ·ΡΡ iCloud/Google, ΠΏΡΠΈΡΠ»Π°ΡΡ ΠΊΠΎΠ΄/ΠΏΠ°ΡΠΎΠ»Ρ, Π·Π°ΠΏΡΡΡΠΈΡΡ ΠΊΠΎΠ΄/ΠΠ, Π½Π΅ Π΄Π΅Π»Π°ΠΉΡΠ΅ ΡΡΠΎΠ³ΠΎ - ΡΡΠΎ ΠΌΠΎΡΠ΅Π½Π½ΠΈΠΊΠΈ. ΠΠ±ΡΠ·Π°ΡΠ΅Π»ΡΠ½ΠΎ ΠΆΠΌΠΈΡΠ΅ "ΠΠΎΠΆΠ°Π»ΠΎΠ²Π°ΡΡΡΡ" ΠΈΠ»ΠΈ ΠΏΠΈΡΠΈΡΠ΅ Π² ΠΏΠΎΠ΄Π΄Π΅ΡΠΆΠΊΡ. ΠΠΎΠ΄ΡΠΎΠ±Π½Π΅Π΅ Π² Π³Π°ΠΉΠ΄Π΅ β