Principal Engineer – Physical Design (ASIC)

Location: Penang, Malaysia

Company

hirify.global develops microcontroller, analog, FPGA, connectivity, and power management semiconductors for industrial, automotive, consumer, aerospace and defense, communications, and computing markets.

What you will do

• Perform physical design from layout floorplanning through GDS convergence for advanced technology nodes.
• Translate design complexity into physical design constraints and strategies for PPA and timing convergence.
• Develop floorplanning, placement, routing, clock planning, and power distribution solutions.
• Implement low-power methodologies including power gating, clock gating, and MBR flows.
• Perform and debug logic equivalence checking, physical verification, DRC/LVS closure, and design audits.
• Improve tools, flows, and methodologies while guiding junior team members and collaborating with worldwide project teams.

Requirements

• Bachelor’s or master’s degree in electrical engineering or an equivalent field.
• 6–10 years of ASIC development experience, including multiple complex ASIC or IC tapeouts on VDSM process technology nodes.
• Experience taking large blocks through timing, physical design, DRC, and LVS closure.
• Proficiency with Synopsys ICC/PT, Cadence Innovus, ETS, and Cadence PVS or equivalent tools.
• Knowledge of low-power methodology, static timing analysis, signal and power integrity, synthesis, UNIX/Linux, and HDL including Verilog or VHDL.
• Strong analytical, communication, mentoring, and leadership skills.

Nice to have

• Experience with Design Compiler, Genus, PrimeTime, or equivalent synthesis and static timing analysis tools.

Culture & Benefits

• Full-time position within a 17,000-member global organization.
• Employee development and leadership programs.
• Culture centered on trust, empowerment, respect, diversity, communication, and community.
• Travel requirement of 0%–25%.