Principal Engineer – Physical Design (ASIC)

Location: Penang, Malaysia

Travel: 0–25%

Company

hirify.global develops microcontroller, analog, FPGA, connectivity, and power management semiconductors for industrial, automotive, consumer, aerospace and defense, communications, and computing markets.

What you will do

• Perform physical design from layout floorplanning through GDS convergence.
• Define physical design constraints and strategies to achieve power, performance, and area targets.
• Develop floorplanning, placement, routing, clock, power distribution, and timing-closure solutions.
• Implement low-power flows including power gating, clock gating, and MBR methodologies.
• Perform and debug LEC, DRC/LVS, post-layout verification, and design audits.
• Improve tools, flows, and methodologies while mentoring junior engineers and collaborating with global project teams.

Requirements

• BEng/MEng in Electrical Engineering or equivalent.
• 6–10 years of ASIC development experience, including multiple complex ASIC or IC tapeouts on advanced process nodes.
• Experience taking large blocks through timing, physical design, DRC, and LVS closure.
• Expertise with Synopsys ICC/PT, Cadence Innovus, ETS, and Cadence PVS.
• Knowledge of low-power methodology, static timing analysis, signal integrity, and power integrity.
• Strong scripting experience with TCL, Perl, and Shell, plus working knowledge of Verilog, VHDL, and Unix/Linux.

Nice to have

• Knowledge of synthesis tools such as Design Compiler or Genus.
• Experience with PrimeTime or equivalent static timing analysis tools.

Culture & Benefits

• Values-based culture focused on trust, empowerment, respect, diversity, and communication.
• Structured leadership and employee development programs.
• Opportunity to work within a global semiconductor organization and collaborate with worldwide project teams.