6 часов назад
Senior FPGA Design/Verification Engineer
Мэтч & Сопровод
Для мэтча с этой вакансией нужен Plus
Описание вакансии
Текст:
TL;DR
Senior FPGA Design/Verification Engineer (Verilog/SystemVerilog): Designing and verifying FPGA control and datapath logic for next-generation optical switches and amplifiers with an accent on simulation environments, synthesis, timing analysis, and lab validation. Focus on integrating IP cores, building automated verification and test infrastructure, debugging cross-functional hardware and firmware systems, and optimizing designs for robust timing performance.
Location: Ottawa, Ontario, Canada; onsite
Company
develops optical and photonic products, including telecommunications products such as optical switches and amplifiers, as well as technologies for cloud networking and industrial applications.
What you will do
- Design FPGA control and datapath logic and configure and integrate IP cores.
- Develop and maintain simulation environments, scripts, testbenches, test cases, and bus functional models.
- Define and execute verification plans and automated testing.
- Collaborate with hardware and firmware engineers on cross-functional integration, lab validation, debugging, and system-level performance.
- Implement synthesis constraints, analyze build and timing reports, and optimize designs for robustness.
- Document designs and tests, mentor junior engineers, and contribute to design reviews and engineering best practices.
Requirements
- Strong experience designing and simulating ASICs or FPGAs using Verilog and SystemVerilog.
- Strong experience with synthesis, constraints, timing analysis, and clock domain crossing.
- Strong problem-solving, troubleshooting, and debugging skills.
- Clear, robust, and well-commented coding style with strong attention to detail.
- Effective verbal and written communication and the ability to collaborate across functional groups.
Nice to have
- Experience with AMD/Xilinx or Altera FPGAs and tools.
- Experience with constrained-random verification, SystemVerilog Assertions, and advanced UVM methodologies.
- Experience with embedded processor SoC design, PCIe, DDR memory, or AXI interfaces.
- Knowledge of digital signal processing concepts.
- Experience with VHDL, C, Csh, Tcl, Python, Perl, or Linux development environments.
Culture & Benefits
- Full-time, permanent employment in a multidisciplinary R&D engineering team.
- Flexible time off and physical and mental health benefits.
- Tuition reimbursement and career growth support.
- Free gym, games room, prayer room, subsidized meals, and complimentary coffee and tea.
- Employee stock options, incentive plans, and a collaborative, innovative, and inclusive workplace.
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