Назад
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9 часов назад

Staff/Sr. Staff Design Verification Engineer

148 000 - 175 000CAD
Формат работы
hybrid
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
Canada
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

Текст:
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TL;DR
Staff/Sr. Staff Design Verification Engineer (UVM/SystemVerilog/AMS): Verifying integrated digital, analog, and photonic devices for AI data center infrastructure with an accent on mixed-signal simulation, emulation, and scalable verification environments. Focus on creating test plans, closing coverage for block-level and full-chip designs, integrating analog IP, and validating performance against system requirements.

Location: Toronto, ON; flexible hybrid workplace model

Salary: Staff: $148,000–$175,000 CAD; Sr. Staff: $203,000–$224,000 CAD

Company

hirify.global develops photonics-based infrastructure for AI and high-performance computing data centers, including 3D-stacked photonics engines for connecting large numbers of processors.

What you will do

  • Define and improve design verification methodologies for integrated digital, analog, and photonic devices, with emphasis on emulation.
  • Create and execute test plans for high-quality tapeouts that meet functional and performance goals.
  • Collaborate with architects, digital designers, analog and photonic designers, and verification engineers to define validation flows.
  • Build reusable, scalable UVM testbench components and verification environments for simulation and emulation.
  • Verify block-level and full-chip designs, close coverage, and complete design verification signoff requirements.
  • Integrate analog IP and develop behavioral models, test cases, and checkers for upper-level designs.

Requirements

  • Bachelor’s degree in Electrical Engineering, Computer Engineering, a related field, or equivalent experience.
  • At least 8 years of design verification and SystemVerilog experience.
  • At least 2 years of Python experience.
  • Expertise with the UVM library.
  • Experience with Xcelium, ModelSim, Questa, or VCS simulators.
  • Strong problem-solving and collaboration skills; candidates must be able to comply with federally mandated U.S. export control requirements.

Nice to have

  • Master’s degree or higher in Electrical Engineering, Computer Engineering, a related field, or equivalent experience with 6 years of relevant experience.
  • Experience with post-silicon validation and debug.
  • Experience with AMS verification.

Culture & Benefits

  • Comprehensive medical, dental, and vision coverage.
  • Retirement savings matching, life insurance, and short- and long-term disability coverage.
  • Vacation, sick leave, public holidays, and paid family leave.
  • Training and development support and commuter benefits.
  • Equity grants for full-time employees and a flexible hybrid workplace model.

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