Static Timing Analysis (STA) Engineer (FPGA)

Location: Toronto, Ontario, Canada

Salary: CAD 102,900–149,100 per year, plus performance-based incentive opportunities.

Company

hirify.global develops advanced FPGA technologies and design solutions.

What you will do

• Perform static timing analysis for FPGA designs, including setup and hold checks, constraint validation, and timing signoff support.
• Identify, debug, and resolve timing violations with RTL, synthesis, and physical design teams.
• Develop and validate timing constraints that accurately model design intent.
• Collaborate with design, architecture, and implementation teams to improve timing convergence.
• Apply STA methodologies and contribute to flow improvements and automation.
• Support performance, power, and area optimization through timing-driven analysis.

Requirements

• 6+ years of experience in static timing analysis for ASIC or FPGA designs.
• Strong understanding of STA fundamentals, including setup and hold checks, timing paths, clocking, and CDC basics.
• Experience with industry-standard tools such as PrimeTime or equivalent, plus synthesis and place-and-route flows.
• Working knowledge of RTL design with Verilog or SystemVerilog and FPGA or ASIC design methodologies.
• Ability to analyze timing reports, identify root causes, and propose actionable solutions.
• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field; eligibility for required Canadian export authorizations.

Nice to have

• Experience with FPGA architectures and timing flows.
• Familiarity with advanced process nodes or high-speed designs.
• Scripting experience with Tcl or Python for automation.
• Experience in large-scale or distributed engineering environments.

Culture & Benefits

• Full-time regular employment.
• Performance-based incentive opportunities tied to individual and company success.
• Canadian work experience is not required.
• Shift 1 schedule in Canada.