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8 часов назад

FPGA Development Tools Engineer – Synthesis (FPGA)

129 100 - 187 000CAD
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
Canada
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Текст:
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TL;DR
FPGA Development Tools Engineer – Synthesis (FPGA): Developing and optimizing synthesis capabilities that transform RTL designs into efficient gate-level implementations for advanced FPGA platforms with an accent on performance, power, area, and compiler toolchain integration. Focus on building scalable synthesis algorithms, analyzing complex RTL, improving quality of results, and integrating synthesis with placement, routing, and timing analysis.

Location: Toronto, Ontario, Canada

Salary: 129.1K–187.0K CAD annually, plus performance-based incentive opportunities.

Company

hirify.global develops programmable FPGA solutions and compiler tools for AI, cloud computing, networking, and edge applications.

What you will do

  • Design, implement, and optimize synthesis algorithms that convert Verilog, SystemVerilog, and VHDL RTL into efficient gate-level representations.
  • Contribute to the FPGA compiler flow by integrating synthesis with placement, routing, and static timing analysis.
  • Improve quality of results across performance, power, and area through synthesis-driven optimization.
  • Develop tools and methodologies for analyzing and transforming complex RTL designs.
  • Debug timing, logic-structure, and mapping issues and drive their resolution with architecture, STA, placement, routing, and validation teams.
  • Build scripting, automation, and internal tooling to improve synthesis flows and engineering productivity.

Requirements

  • 6+ years of experience in FPGA or ASIC design, EDA tools, or related fields.
  • Strong hands-on experience with RTL design and synthesis flows using Verilog, SystemVerilog, or VHDL.
  • Proficiency in C/C++ and strong knowledge of algorithms and data structures.
  • Understanding of logic synthesis, optimization, FPGA or ASIC design flows, and timing-driven design.
  • Experience with debugging and performance analysis, plus the ability to develop scalable, high-performance solutions.
  • Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field; relevant doctoral-study experience may count toward the experience requirement.

Nice to have

  • Experience with Quartus, Vivado, or other synthesis tools and FPGA toolchains.
  • Knowledge of FPGA architectures, including LUTs, DSPs, BRAM, and interconnect.
  • Experience with retiming, logic restructuring, resource sharing, Python, Tcl, compiler development, or EDA algorithms.
  • Experience working in large, distributed engineering teams.

Culture & Benefits

  • Opportunity to build core synthesis technology for next-generation FPGA platforms.
  • Influence compiler architecture and performance at scale.
  • Collaboration with engineers across silicon, architecture, and software.
  • Canadian work experience is not required.
  • Applicants must be eligible for any required Canadian export authorizations.

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