Назад
Company hidden
1 день назад

Technical Lead IC Design/Principal - Micro-architecture, RTL Design

145 800 - 194 400CAD
Тип работы
fulltime
Грейд
senior/lead
Английский
b2
Страна
Canada
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
Для мэтча и отклика нужен Plus

Мэтч & Сопровод

Для мэтча с этой вакансией нужен Plus

Описание вакансии

Текст:
/
TL;DR
Technical Lead IC Design/Principal - Micro-architecture, RTL Design (ASIC/DSP): Developing high-speed optical Ethernet transceiver ASICs with an accent on micro-architecture, Verilog/SystemVerilog RTL implementation, synthesis, and verification. Focus on timing closure, power and latency optimization, post-silicon debug, and validating DSP functionality from system models through laboratory bring-up.

Location: Ottawa, Canada

Expected base pay: CAD 145,800–194,400 per annum

Company

hirify.global develops semiconductor solutions for enterprise, cloud, AI, automotive, and carrier data infrastructure.

What you will do

  • Implement high-speed data-path RTL for optical Ethernet transceiver ASICs using Verilog.
  • Develop ASIC specifications and micro-architectures for signal-processing and communications algorithms.
  • Integrate vendor IP and support synthesis, backend resources, timing closure, and customer deployment.
  • Perform static timing analysis, formal equivalence, RTL lint, CDC analysis, and functional verification.
  • Debug and correlate post-silicon results, support chip bring-up, and validate functionality in the lab.
  • Mentor junior team members and assist with CAD/EDA flow automation.

Requirements

  • Bachelor’s degree in Electrical Engineering or a related field and 10+ years of related professional experience.
  • Experience across the complete ASIC design cycle, from micro-architecture and Verilog coding through constraints, synthesis, LEC, timing closure, post-silicon debug, and lab support.
  • Experience with block- and subsystem-level RTL development, gate-level verification, and debug.
  • Experience matching DSP block-model functionality with RTL and performing synthesis, static timing analysis, and functional verification.
  • Strong system-level modeling, debugging, troubleshooting, communication, and presentation skills.
  • Strong proficiency in Verilog, SystemVerilog, Python, and Unix Shell; ability to multitask in a rapidly changing environment.

Nice to have

  • Experience with high-speed IEEE-compliant DSP physical-layer products.

Culture & Benefits

  • Collaborative and transparent work environment focused on inclusive teamwork.
  • Competitive compensation and benefits.
  • Resources and support for professional growth and development.
  • Interview candidates may not use AI tools, transcription apps, automated note-taking bots, or real-time answer generators during interviews.
  • Access to export-controlled technology may require an export license review under U.S. regulations.

Будьте осторожны: если работодатель просит войти в их систему, используя iCloud/Google, прислать код/пароль, запустить код/ПО, не делайте этого - это мошенники. Обязательно жмите "Пожаловаться" или пишите в поддержку. Подробнее в гайде →