Sr. Staff SoC RTL Engineer

Location: Austin, Texas, United States; onsite five days per week. Candidates must be currently authorized to work in the United States.

Company

hirify.global develops ultra-low-power semiconductor solutions, including MCUs and SoCs for wearables, medical devices, connected sensors, IoT products, and AI-powered edge applications.

What you will do

• Define microarchitectures for digital SoC modules and subsystems.
• Develop production-quality RTL using Verilog and SystemVerilog.
• Own complex blocks from specification through pre-tapeout signoff.
• Integrate internal and third-party IP into ARM-based MCU and SoC platforms using AMBA interconnects.
• Partner with verification and physical design teams on test planning, coverage closure, timing, power, area, and implementation issues.
• Support LINT, CDC, and RDC analysis, FPGA prototyping, tapeout, silicon bring-up, and post-silicon debug while mentoring engineers.

Requirements

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
• At least 8 years of hands-on ASIC or SoC RTL design experience.
• Strong Verilog and/or SystemVerilog development skills.
• Experience with architecture and microarchitecture specifications, synthesis, timing, LINT, CDC, and RDC.
• Experience working with verification and physical design teams through design closure, tapeout, silicon bring-up, or post-silicon debug.
• Familiarity with ARM-based SoCs and AMBA protocols such as AHB, APB, or AXI.

Nice to have

• ARM Cortex-M or embedded CPU subsystem integration experience.
• Experience with MCU architecture, peripheral integration, memory maps, DMA, interrupt controllers, or bus arbitration.
• Low-power SoC design experience involving UPF, power gating, clock gating, retention, or multi-voltage domains.
• Experience with memory controllers, DSPs, hardware accelerators, security blocks, AI-related IP, FPGA prototyping, or emulation.
• Multiple successful production tapeouts and third-party IP evaluation or integration experience.

Culture & Benefits

• Ownership of meaningful portions of products shipped in high-volume customer applications.
• Opportunity to influence architecture before designs are locked.
• Collaboration across the full silicon lifecycle and directly with senior technical leaders.
• Hands-on work addressing power and performance challenges in edge computing.