14 часов назад
Principal Engineer - Design (FPGA)
Мэтч & Сопровод
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Описание вакансии
Текст:
TL;DR
Principal Engineer - Design (FPGA) (FPGA/USB/Ethernet PHY): Developing, integrating, and validating FPGA-based platforms for next-generation USB and Ethernet PHY products with an accent on synthesizable RTL, multi-clock-domain design, and system-level integration. Focus on optimizing FPGA performance and resource utilization, debugging physical circuit cards, and automating simulation, synthesis, and implementation flows.
Location: Chandler Design Center, Chandler, Arizona, United States
Company
develops semiconductor products and technology solutions used in embedded and connected systems.
What you will do
- Develop, integrate, and validate FPGA-based platforms supporting mixed-signal IP and SoC products.
- Support PHY development for next-generation USB and Ethernet products.
- Implement synthesizable RTL, including datapaths, state machines, pipelines, FIFOs, memories, clocking, resets, and interface logic.
- Perform simulation, synthesis, timing analysis, place-and-route, and FPGA implementation using vendor design environments.
- Integrate FPGA systems and bring up boards by loading FPGA images, testing hardware interfaces, and debugging physical circuit cards.
- Collaborate with digital, analog, hardware, firmware, software, ASIC, verification, and validation teams.
Requirements
- 10 or more years of experience in FPGA and/or digital design.
- Strong proficiency in Verilog and/or SystemVerilog for synthesizable RTL design.
- Hands-on experience with self-checking testbenches, functional simulation, and debug using QuestaSim, ModelSim, or equivalent tools.
- Experience with FPGA synthesis, implementation, timing constraints, multiple clock domains, timing analysis, and place-and-route using tools such as AMD/Xilinx Vivado.
- Experience with FPGA system integration, board-level bring-up, laboratory debug equipment, and embedded FPGA logic-debug tools.
- Ability to document requirements, FPGA architecture, block diagrams, interface control documents, and technical designs; scripting or programming experience with TCL, Python, Perl, Linux shell, C++, or Rust is required.
Nice to have
- Experience with USB and Ethernet PHY architectures and protocols.
- Knowledge of Perforce, Git, DesignSync, or equivalent revision-control systems.
Culture & Benefits
- Full-time employment within a 17,000-member global organization.
- Structured leadership and career-development programs.
- Values-based decision-making, employee development, diversity, and workplace community.
- Travel requirement of 0%–25%.
- Physical requirements include approximately 80% sitting, 10% standing, and 10% walking.
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