Senior RTL Design Engineer (RISC-V)

Location: Sunnyvale, California, United States

Company

hirify.global.

What you will do

• Architect and implement new features, performance improvements, and ISA extensions in RISC-V CPU core generators.
• Develop and specify CPU microarchitecture while documenting design decisions and sharing technical knowledge.
• Perform initial sandbox verification and collaborate with the design verification team on comprehensive test plans.
• Work with the physical implementation team to optimize designs for frequency, area, and power targets.
• Collaborate with performance modeling specialists on performance exploration and optimization.

Requirements

• 8+ years of recent industry experience designing high-performance, energy-efficient CPUs.
• Expertise in CPU processor design, including areas such as instruction fetch and decode, branch prediction, register renaming, instruction scheduling, execution units, load-store units, or cache and memory subsystems.
• Proficiency in RTL design using Verilog, SystemVerilog, or VHDL.
• Successful CPU development experience from architecture through tapeout.
• MS or PhD in electrical engineering, computer engineering, computer science, or a related technical discipline, or equivalent experience.
• Ability to collaborate effectively and contribute to high-quality engineering design.

Nice to have

• Knowledge of RISC-V architecture.
• Experience with Scala or Chisel.
• Knowledge of at least one object-oriented or functional programming language.