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6 часов назад

Quality and Reliability Engineer (Semiconductor)

Формат работы
hybrid
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

Текст:
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TL;DR
Quality and Reliability Engineer (Semiconductor): Establishing company-wide quality, reliability, and design-for-reliability systems for chiplet solutions powering next-generation AI and advanced computing, with an accent on semiconductor qualification, supplier quality, and predictive reliability modeling. Focus on planning stress tests, assessing failure mechanisms such as TDDB, BTI, HCI, EM, and SM, and driving risk mitigation from product development through high-volume manufacturing.

Location: Chandler, Arizona, United States; hybrid with 3 days per week onsite. Headquarters are in Vancouver, Washington.

Company

hirify.global is a well-funded semiconductor startup developing chiplet solutions for high-performance chips used in AI and advanced computing.

What you will do

  • Own company-wide quality, reliability, and design-for-reliability initiatives from development through high-volume manufacturing.
  • Define process quality and reliability requirements with wafer foundries, OSAT partners, and internal design teams.
  • Manage supplier qualifications, test vehicles, manufacturing quality improvements, and pre-tape-out risk mitigation.
  • Lead product bring-ups, qualification activities, excursion-material disposition, and product return evaluations.
  • Plan and execute stress testing with partners to build predictive models for intrinsic and extrinsic failure mechanisms.
  • Establish quality guidelines, qualification standards, and reliability frameworks for next-generation product architectures.

Requirements

  • PhD or MS in Electrical Engineering, Physics, Materials Science, or a related field.
  • 8+ years of hands-on experience in semiconductor process, quality management, and product reliability.
  • Deep knowledge of semiconductor physics, acceleration models, and wear-out mechanisms, including TDDB, BTI, HCI, EM, and SM.
  • Experience with wafer-level reliability testing, test structures, and industry standards including JEDEC, AEC-Q100, and ISO 9001.
  • Expertise in quality and reliability statistics, JMP, SPC charting, and failure-rate calculations across the bathtub curve.
  • Knowledge of semiconductor defect analysis, root-cause failure analysis, 8D problem solving, defect screening, and degradation mechanisms in logic, memory, and analog circuits.

Culture & Benefits

  • Full-time role within the Engineering department.
  • Cross-functional collaboration with design teams, foundries, OSAT partners, suppliers, and executive leadership.
  • Hands-on work across semiconductor development, qualification, and manufacturing.

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