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7 часов назад

Sr. Staff Engineer - DFT (Semiconductor)

Формат работы
onsite
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
Singapore/US/China +1 еще
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Мэтч & Сопровод

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Описание вакансии

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TL;DR
Sr. Staff Engineer - DFT (Semiconductor): Designing and optimizing low-power DFT architectures for ultra-low-power SoCs, including scan insertion, boundary scan, MBIST, and ATPG, with an accent on test coverage, test time, and manufacturing efficiency. Focus on developing hierarchical test infrastructure, generating and diagnosing structural test patterns, running pre-/post-layout simulations, and bringing up production test vectors on silicon.

Location: On-site 5 days a week in NW Austin, Texas, United States

Company

hirify.global develops ultra-low-power semiconductor solutions for wearables, medical devices, IoT products, and AI-powered edge applications.

What you will do

  • Own DFT strategy and develop low-power test architectures for ultra-low-power SoCs.
  • Implement scan insertion, boundary scan, MBIST, and ATPG using standard EDA tools.
  • Generate structural test vectors and improve test coverage, test time, and test cost.
  • Perform pre- and post-layout scan and MBIST simulations.
  • Collaborate with design teams on timing, physical, power, and logical DFT issues.
  • Work with test engineering teams to bring up production test vectors on silicon.

Requirements

  • BS/MS in Electrical Engineering, Electronics Engineering, or a related field, with 10+ years of DFT implementation experience.
  • Required hands-on expertise with Cadence Genus and Modus Compression for low-power scan insertion and ATPG pattern generation.
  • Strong knowledge of scan testing, scan compression, boundary scan, MBIST, hierarchical DFT architectures, and memory test strategies.
  • Experience with Tessent MBIST memory repair patterns, test coverage and test time optimization, ATPG/MBIST testbenches, and pre-/post-layout simulation.
  • Experience analyzing ATE failure data, performing ATPG diagnosis, and collaborating on production test programs.
  • Working knowledge of RTL design and verification, timing analysis, constraint development, Tcl, and gate-level simulation; Perl and/or Python experience is preferred.

Culture & Benefits

  • Cross-functional work across design, research, development, production, marketing, sales, and operations.
  • Work focused on energy efficiency and semiconductor technology for edge AI and IoT applications.
  • Company values include innovation, collaboration, focus, learning, and achievement.
  • Candidates must be authorized to work in the United States.
  • Valid EAD work authorization is accepted; H-1B transfers may be considered for candidates with an approved I-140.
  • No new H-1B sponsorship is available for this role.

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