Senior DfT Engineer (Semiconductors)

Location: Chandler, Arizona, United States; minimum three full days per week in the NXP Chandler office. Willingness to relocate to the Phoenix Metro area is required.

Company

hirify.global develops semiconductor solutions.

What you will do

• Collaborate with product definition, analog and digital design, test, product engineering, quality, and validation specialists to define chip testability requirements.
• Develop DfT architectures and high-quality RTL for complex analog, mixed-signal, standard memory, converter, and digital IPs.
• Define verification plans, write tests, debug failures, and achieve passing results in the chip-level design verification environment.
• Perform scan insertion, optimization, chain length balancing, P&R-aware rerouting, test-point insertion, and ATPG pattern generation and simulation.
• Support silicon pattern debug, customer-return investigations, design and test reviews, and DfT issue resolution.
• Create and maintain DfT architecture and design documentation throughout product development.

Requirements

• Master’s degree in electrical engineering with coursework focused on digital design, RTL coding, DfT, computer architecture, and digital verification.
• Three to eight years of total experience, including at least three years in DfT, digital design, and architecture roles.
• Experience with Verilog and SystemVerilog RTL design.
• Strong problem-solving, teamwork, planning, organization, attention to detail, and communication skills.
• Must be willing to relocate to the Phoenix Metro area and work from the Chandler office at least three full days per week.

Culture & Benefits

• Work within a highly experienced DfT engineering team.
• Collaborate across product definition, design, test, quality, validation, and product engineering functions.
• Participate in design and test review meetings.
• Stay current with DfT industry trends, tools, and methodologies.