Senior DfT Engineer (Verilog)

TL;DR

Senior DfT Engineer (Verilog/System-Verilog): Developing and implementing Design for Test (DfT) architectures for complex analog and mixed-signal IPs and digital logic with an accent on RTL design, scan insertion, and ATPG pattern generation. Focus on optimizing testability, resolving silicon debug issues, and ensuring high-quality verification at the chiptop level.

Location: Chandler, Arizona. Must be based in or be able to relocate to the Phoenix Metro area and be present in the office minimum 3 days per week.

Company

A global semiconductor leader specializing in secure connectivity solutions for embedded applications and automotive electronics.

What you will do

• Collaborate with design and test leads to define testability requirements for Functional mode, Debug mode, and ATPG.
• Implement DfT for complex analog/mixed-signal IPs, standard macros, and digital logic using Verilog and System-Verilog.
• Develop verification plans, write tests, and debug features at the chiptop level DV environment.
• Perform scan insertion, optimization, chain rerouting, and ATPG pattern generation and simulation.
• Support test engineers during silicon debug of patterns and customer return analysis.
• Generate and maintain comprehensive DfT architecture and design documentation.

Requirements

• Master's degree (MSEE) in Digital Design, RTL coding, DfT, or Computer Architecture.
• 3-8 years of professional experience in DfT, Digital Design, and Architecture.
• Willingness to relocate to the Phoenix Metro area (Arizona).
• Minimum 3 days per week full-day presence in NXP's Chandler office.
• Strong problem-solving, teamwork, and communication skills.