DFT Design Engineer

Location: San Jose, California, United States

Salary: $149,100–$213,015 USD per year for the Bay Area, California

Company

hirify.global provides programmable logic solutions including FPGAs, SoCs, CPLDs, IP, development tools, SmartNICs, and IPUs for applications from the cloud to the edge.

What you will do

• Define and implement DFT architectures and specifications for FPGA, processor, DSP, SERDES, IO, and multi-die designs.
• Insert test logic, generate ATPG patterns, and perform pre-silicon validation.
• Collaborate with IP and integration design teams to align DFT features with circuit functionality and timing.
• Support silicon bring-up, debug, manufacturing test, and production readiness.
• Develop DFT methodologies and automation flows to improve scalability and validation efficiency.
• Optimize test coverage, test cost, yield, and manufacturability.

Requirements

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related field with 7+ years of industry experience, or a master’s degree with 5+ years.
• Experience in DFT design and verification at RTL and gate level.
• Experience with synthesis, scan insertion, ATPG, simulation, debug, and STA tools.
• Design automation experience and proficiency in Perl or TCL scripting.
• Applicants must be eligible for any required U.S. export authorizations.

Nice to have

• Experience with test compression, MBIST, LBIST, and advanced fault models.
• Experience with 2.5D/3D multi-die designs and high-speed IO or SerDes DFT.

Culture & Benefits

• Opportunity to work on advanced FPGA, processor, DSP, SERDES, IO, and multi-die technologies.
• Collaboration with IP, integration design, and test development teams.
• Incentive opportunities based on individual and company performance.
• Regular full-time employment.