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1 день назад

Principal DFT Engineer (AI)

180 000 - 255 000$
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

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TL;DR
Principal DFT Engineer (AI): Building and testing high-performance RDU chips for machine learning and artificial intelligence with an accent on DFT architecture, ATPG, MBIST, and silicon bring-up. Focus on developing hierarchical SoC test infrastructure, generating production ATPG patterns, closing DFT timing, and diagnosing silicon failures.

Location: Austin, Texas, United States or San Jose, California, United States

Salary: $180,000–$255,000 USD base salary per year

Company

hirify.global develops a full-stack generative AI platform powered by its SN40L chip for enterprise and government organizations.

What you will do

  • Define and implement block-level and SoC-level DFT architecture for large hierarchical SoCs.
  • Develop and maintain ATPG flows for stuck-at, at-speed, and advanced fault models.
  • Build scripts and automation for DFT insertion, ATPG, coverage analysis, pattern generation, and debug.
  • Develop and maintain JTAG, IEEE 1500, and IEEE 1687/IJTAG infrastructure for internal test and debug access.
  • Generate production-quality ATPG and MBIST patterns and support deployment to ATE.
  • Collaborate with STA and Physical Design teams on DFT timing closure, silicon diagnosis, failure localization, yield analysis, and manufacturing test optimization.

Requirements

  • Bachelor’s degree in computer science, computer engineering, or a related field.
  • 10+ years of relevant industry experience.
  • Deep understanding of scan insertion, scan compression, ATPG, MBIST, JTAG, and hierarchical DFT.
  • Hands-on experience with Siemens Tessent or equivalent industry-standard DFT tools.
  • Strong understanding of advanced ATPG, silicon diagnosis, and failure localization methodologies.
  • Experience with STA constraints and analysis for DFT modes, SDF simulations, Verilog/SystemVerilog simulators, and waveform debugging.

Nice to have

  • Experience with cell-aware ATPG, small-delay defects, IEEE 1500, IEEE 1687/IJTAG, and low-power DFT.
  • Experience with ATE pattern deployment and silicon bring-up.
  • Experience with multi-die/chiplet DFT, known-good-die testing, or die-to-die interface testing.
  • Experience with large compute, AI accelerator, or HPC SoCs.

Culture & Benefits

  • Full-time US employment with base salary, equity, and benefits.
  • Medical insurance with 95% premium coverage for employees and 77% coverage for dependents.
  • Health Savings Account with employer contribution, plus dental, vision, disability, life, AD&D, and flexible spending account options.
  • Well-being benefits including Headspace, Gympass+, One Medical, and employee counseling services.
  • Equal opportunity employment.

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