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Senior Director - SoC Front End Engineering (Edge AI)

Π€ΠΎΡ€ΠΌΠ°Ρ‚ Ρ€Π°Π±ΠΎΡ‚Ρ‹
onsite
Π’ΠΈΠΏ Ρ€Π°Π±ΠΎΡ‚Ρ‹
fulltime
Π“Ρ€Π΅ΠΉΠ΄
director
Английский
b2
Π‘Ρ‚Ρ€Π°Π½Π°
Singapore/US/China +1 Π΅Ρ‰Π΅
Вакансия ΠΈΠ· списка Hirify.GlobalВакансия ΠΈΠ· Hirify Global, списка ΠΌΠ΅ΠΆΠ΄ΡƒΠ½Π°Ρ€ΠΎΠ΄Π½Ρ‹Ρ… tech-ΠΊΠΎΠΌΠΏΠ°Π½ΠΈΠΉ
Для мэтча ΠΈ ΠΎΡ‚ΠΊΠ»ΠΈΠΊΠ° Π½ΡƒΠΆΠ΅Π½ Plus

ΠœΡΡ‚Ρ‡ & Π‘ΠΎΠΏΡ€ΠΎΠ²ΠΎΠ΄

Для мэтча с этой вакансиСй Π½ΡƒΠΆΠ΅Π½ Plus

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TL;DR
Senior Director - SoC Front End Engineering (Edge AI): Leading the front-end design and implementation of ultra-low-power Edge AI MCU SoCs, including CPU subsystems, neural accelerators, security, memory, and peripheral integration, with an accent on power-optimized AI compute, RTL design, verification, and production execution. Focus on building a world-class engineering organization, driving PPA optimization and first-silicon success, and delivering multiple MCU programs from architecture through tapeout.

Location: On-site 5 days a week in NW Austin, Texas, United States. Candidates must be currently authorized to work in the United States for any employer.

Company

hirify.global develops ultra-low-power semiconductor solutions for wearables, medical devices, IoT products, and AI-powered edge applications.

What you will do

  • Lead front-end design for Edge AI MCU platforms, including CPU subsystems, neural accelerators, security, memory, and peripheral integration.
  • Guide architecture definition, RTL design, subsystem integration, verification, lint, CDC, and DFT readiness.
  • Drive multiple MCU programs from concept through production tapeout, including milestones, deliverables, risk management, design reviews, and sign-off.
  • Partner with architecture, physical design, analog/mixed-signal, validation, operations, test, and product engineering teams on PPA, yield, manufacturability, and software-hardware performance.
  • Evaluate EDA tools, design automation, and verification infrastructure to improve tapeout readiness.
  • Lead and grow front-end design, verification, and integration teams while mentoring senior technical staff.

Requirements

  • 20+ years of semiconductor front-end design and verification experience, including 15+ years in leadership roles managing multidisciplinary teams.
  • Proven delivery of MCU, SoC, or ASIC products into high-volume production.
  • Expertise in low-power digital design, including multi-voltage domains, power gating, and clock management.
  • Hands-on knowledge of SystemVerilog, UVM, synthesis, and static timing analysis methodologies.
  • Familiarity with ARM Cortex-M/R/A or RISC-V architectures and AHB/AXI on-chip interconnects.
  • BS or MS in Electrical or Computer Engineering required; PhD preferred.

Nice to have

  • Experience with subthreshold or near-threshold design techniques and power modeling.
  • Knowledge of EDA flows for advanced process nodes at 16nm and below.

Culture & Benefits

  • Work in cross-functional teams spanning design, research, development, production, marketing, sales, and operations.
  • Build a culture of technical excellence, collaboration, and accountability.
  • Contribute to ultra-low-power semiconductor technology for AI at the edge.
  • Visa sponsorship and transfer of employment visa sponsorship are not available for this role.

Π‘ΡƒΠ΄ΡŒΡ‚Π΅ остороТны: Ссли Ρ€Π°Π±ΠΎΡ‚ΠΎΠ΄Π°Ρ‚Π΅Π»ΡŒ просит Π²ΠΎΠΉΡ‚ΠΈ Π² ΠΈΡ… систСму, ΠΈΡΠΏΠΎΠ»ΡŒΠ·ΡƒΡ iCloud/Google, ΠΏΡ€ΠΈΡΠ»Π°Ρ‚ΡŒ ΠΊΠΎΠ΄/ΠΏΠ°Ρ€ΠΎΠ»ΡŒ, Π·Π°ΠΏΡƒΡΡ‚ΠΈΡ‚ΡŒ ΠΊΠΎΠ΄/ПО, Π½Π΅ Π΄Π΅Π»Π°ΠΉΡ‚Π΅ этого - это мошСнники. ΠžΠ±ΡΠ·Π°Ρ‚Π΅Π»ΡŒΠ½ΠΎ ΠΆΠΌΠΈΡ‚Π΅ "ΠŸΠΎΠΆΠ°Π»ΠΎΠ²Π°Ρ‚ΡŒΡΡ" ΠΈΠ»ΠΈ ΠΏΠΈΡˆΠΈΡ‚Π΅ Π² ΠΏΠΎΠ΄Π΄Π΅Ρ€ΠΆΠΊΡƒ. ΠŸΠΎΠ΄Ρ€ΠΎΠ±Π½Π΅Π΅ Π² Π³Π°ΠΉΠ΄Π΅ β†’