Manager/Director of Hardware Engineering

Location: Santa Clara, California, United States — onsite only

Company

Series B semiconductor startup developing and licensing software-driven unified fabric and interconnect IP for single-die and multi-die systems, including chiplet-based SoCs.

What you will do

• Lead, mentor, and grow a team of 8–12 RTL microarchitects and design verification engineers.
• Drive high-speed interconnect IP development from microarchitecture specifications through RTL implementation and tape-out.
• Oversee coverage-driven verification plans, UVM/OVM environments, and emulation platforms.
• Collaborate with architecture, physical design, and system engineering teams to balance power, performance, area, and timing requirements.
• Define engineering metrics, standard methodologies, and agile project management practices for strict tape-out milestones.

Requirements

• B.S. or M.S. in Electrical Engineering, Computer Engineering, or a related field.
• 8+ years of industry experience in ASIC or IP development, including 2–3 years in technical leadership or management.
• Strong experience with high-speed protocols such as PCIe, UCIe, CXL, Ethernet, or advanced SerDes.
• Proficiency in SystemVerilog, Verilog, and industry-standard EDA simulation and synthesis flows.
• Deep knowledge of UVM/OVM, constrained-random testing, formal verification, and coverage analysis.
• Adaptability, proactive problem-solving, and a track record of delivering results in a fast-moving startup environment.

Culture & Benefits

• Fast-moving Series B startup environment focused on semiconductor innovation.
• Performance incentives and equity.
• Comprehensive medical, dental, and vision benefits.
• 401(k) retirement plan.