Technical Chief of Staff for ASIC Engineering (Semiconductor)

Location: Fully in person in San Jose, California, United States

Salary: $216,000–$300,000 per year, depending on experience, level, and business need; discretionary bonus, incentives, and benefits may be available.

Company

hirify.global provides rack-scale AI infrastructure through semiconductor-based connectivity solutions and software for hyperscalers and ecosystem partners.

What you will do

• Drive the operational cadence for ASIC Engineering, including all-hands meetings, staff meetings, leadership syncs, technical talks, university engagements, and action follow-through.
• Frame and resolve high-leverage technical, operational, and organizational decisions while surfacing blockers and managing escalations.
• Partner with Hardware, Product, and Quality teams to align priorities, communications, and execution.
• Lead status and milestone management for ASIC tapeout programs, including methodology checklists and boundary agreements.
• Track IP deliveries, version inventory, vendor issues, requirements, resources, quality KPIs, and engineering documentation.
• Produce internal status reporting for Silicon Engineering leadership and drive outcomes through influence rather than hierarchy.

Requirements

• 10+ years of experience in semiconductor, SoC, ASIC, or a similarly complex engineering environment.
• Proven success as a Chief of Staff, Staff Program Manager, TPM Director, or in a similar technical leadership-enablement role.
• Strong technical acumen, including the ability to assess engineering trade-offs, make decisions with limited information, challenge assumptions, and build credibility with senior individual contributors.
• Experience running program cadence for complex silicon programs, including tapeout and IP integration.
• Ability to organize complex workflows, drive consistent follow-through, navigate organizational tension, and align diverse viewpoints.
• Exceptional written and verbal communication, structured thinking, execution discipline, and organizational awareness.

Nice to have

• Prior experience leading RTL2GDSII chip design.

Culture & Benefits

• Fully in-person collaboration at the San Jose location.
• Potential eligibility for discretionary bonus, incentives, and benefits.
• Inclusive workplace that encourages applications from people with diverse backgrounds and experiences.