20 часов назад
Chip Lead, Senior Director (UALink)
Мэтч & Сопровод
Для мэтча с этой вакансией нужен Plus
Описание вакансии
Текст:
TL;DR
Chip Lead, Senior Director (UALink): Driving the end-to-end development of next-generation UALink switching products, from architecture and RTL through tapeout, validation, and customer enablement, with an accent on large-scale chip integration, chiplet architectures, and 2.5D/3D advanced packaging. Focus on coordinating design, verification, DFT, physical design, firmware, systems, and operations while ensuring chip quality, timing closure, power optimization, and predictable execution.
Location: San Jose, California, United States, or Israel
Company
develops semiconductor-based connectivity solutions and software for rack-scale AI infrastructure and hyperscale data centers.
What you will do
- Own the full technical lifecycle of UALink switching products, including architecture, design integration, validation, readiness, tapeout, signoff, and customer enablement.
- Drive chip development from RTL to GDSII and ensure architecture, implementation, tapeout, and quality milestones are achieved.
- Lead development of 300–400 mm² chips using 2.5D/3D advanced packaging and chiplet-based architectures.
- Coordinate design verification, DFT, physical design, firmware, systems, and operations to surface and resolve risks and dependencies.
- Guide verification coverage, regression strategies, scan insertion, BIST, manufacturing test, timing closure, and power optimization.
- Establish scalable processes, documentation, decision-making practices, and technical leadership standards across the product line.
Requirements
- Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related field.
- 15+ years of experience across architecture, silicon design, validation, systems, or related domains.
- Proven experience taking large-scale chips of 300 mm² or larger through successful tapeout.
- Hands-on experience with 2.5D/3D advanced packaging, chiplet architectures, RTL design, design verification, DFT, and physical design flows.
- Experience with high-speed serial interfaces such as PCIe or Ethernet and switching architectures.
- Experience leading cross-functional technical programs with end-to-end product ownership, strong communication, and executive presence.
Nice to have
- Master’s degree in Electrical Engineering or Computer Engineering.
- Experience with UALink, UCIe, PCIe Gen5/Gen6/Gen7, or Ethernet switching architectures.
- Experience with 7nm, 5nm, or smaller process nodes.
- Background in power management, clocking architectures, or high-speed analog integration.
- Experience in fast-growing startup or hyperscale environments.
Culture & Benefits
- Emphasis on systems thinking, adaptability, execution discipline, and calm leadership under pressure.
- Focus on ownership, accountability, mentoring, technical judgment, and cross-functional collaboration.
- Commitment to diverse ideas, backgrounds, and experiences in engineering teams.
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