Senior Project Manager for Chip-to-Package Interaction (CPI) Qualifications (Semiconductor)

Location: Onsite at the hirify.global facility in Malta, New York, USA

Salary: $98,000–$176,000 per year

Company

hirify.global is a full-service semiconductor foundry providing design, development, and fabrication services with manufacturing operations across three continents.

What you will do

• Lead end-to-end Chip-to-Package Interaction (CPI) qualification programs from concept through qualification and technology release.
• Define qualification strategies, project scope, milestones, success criteria, test structures, characterization requirements, and data collection plans.
• Manage project schedules, budgets, resources, risks, qualification metrics, reliability results, and technical milestones.
• Coordinate cross-functional teams across technology development, design, reliability engineering, manufacturing, quality, supply chain, and external OSAT partners.
• Lead technical reviews, readiness assessments, qualification reviews, and cross-functional decision-making.
• Communicate qualification strategies, project status, reliability results, risk assessments, and technology readiness to management, customers, and external stakeholders.

Requirements

• Bachelor’s or Master’s degree in Electrical Engineering, Materials Science, Physics, or a related technical discipline.
• Minimum 5 years of experience in the semiconductor industry, including technology development, packaging, assembly, reliability engineering, or qualification.
• Experience leading complex, cross-functional technical projects from concept through qualification and technology release.
• Strong knowledge of semiconductor packaging and post-fab technologies, including bumping, assembly, package-level testing, and OSAT operations.
• Understanding of BEOL process integration, chip-to-package interactions, and semiconductor reliability qualification methodologies.
• Demonstrated schedule, budget, resource, risk, leadership, communication, analytical, and stakeholder-management skills.

Nice to have

• Experience with wirebond, flip-chip, wafer-level packaging, 2.5D/3D integration, TSVs, silicon interposers, or chiplet-based solutions.
• Knowledge of JEDEC and AEC-Q100 qualification and reliability standards.
• Experience working with customers, OSATs, external technology partners, and global semiconductor manufacturing environments.
• PMP certification or an equivalent project management qualification.

Culture & Benefits

• Work with global, cross-functional teams and external semiconductor partners.
• Support Environmental, Health, Safety & Security requirements and programs.
• Employment is subject to applicable pre-employment conditions and laws.
• Reasonable workplace accommodations are considered on a case-by-case basis.