Senior Debug Verification Engineer (FPGA)

Location: San Jose, California, United States

Salary: $149,100–$215,000 USD per year; incentive opportunities may also be available.

Company

hirify.global is an independent FPGA solutions provider developing programmable technologies for AI, cloud, networking, and edge markets.

What you will do

• Verify pre-silicon SoC, FPGA, and full-chip designs.
• Create test cases and UVM-based testbenches.
• Define verification strategies, methodologies, and test plans for full-chip and system functional verification.
• Verify Design for Debug architectures, including JTAG, high-speed USB, PCIe-based debug, and internal signal visualization.
• Use full-system applications to verify performance and identify shortcomings.
• Coordinate coverage verification with Design, Software, and Architecture teams.

Requirements

• 8+ years of experience with complex ASIC designs and/or verification.
• 8+ years of experience with SystemVerilog.
• 8+ years of experience with UVM and formal verification methodologies.
• Experience scripting in Linux or Unix environments; Perl and Python proficiency is desirable.
• Strong communication skills and ability to collaborate with teams across different geographic sites.
• Applicants must be eligible for any required U.S. export authorizations.

Nice to have

• Experience with ARM and RISC debug architectures.
• Experience with UltraSoC or Tessent Embedded Analytics Debug Architecture.
• Emulation experience.

Culture & Benefits

• Full-time regular employment.
• Incentive opportunities based on individual and company performance.
• Collaboration across geographically distributed teams.
• Use of artificial intelligence in applicant screening, assessment, or selection.