Senior Design Verification Engineer (PCIe/UALink)

Location: San Jose, California, United States

Salary: $148,500–$165,000 per year, depending on experience, level, and business need. The role may also include discretionary bonuses, incentives, and benefits.

Company

hirify.global develops semiconductor-based connectivity solutions and software for rack-scale AI infrastructure, including PCIe, CXL, Ethernet, NVLink, and UALink technologies.

What you will do

• Develop block- and subsystem-level verification plans from specifications, architecture, and design requirements.
• Build reusable UVM-based SystemVerilog testbenches, agents, sequences, monitors, and reference models.
• Create directed and constrained-random scenarios for PCIe Gen 6/Gen 7, UALink, and UCI behavior.
• Define coverage models, checkers, assertions, and scoreboards for complex switching functionality.
• Analyze simulation failures, waveforms, logs, assertions, and regression results to identify root causes.
• Drive coverage closure and partner with design and post-silicon teams on issue isolation and silicon bring-up readiness.

Requirements

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related technical field.
• 2–5 years of design verification experience with complex ASICs or SoCs.
• Hands-on experience with SystemVerilog and UVM-based verification environments.
• Experience developing verification plans, testbenches, assertions, scoreboards, and functional coverage models.
• Familiarity with simulation, waveform debugging, regression, and coverage tools.
• Strong debugging, communication, and collaboration skills in a fast-paced product development environment.

Nice to have

• Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
• Experience verifying PCIe, UALink, UCI, or other high-speed connectivity and switching protocols.
• Knowledge of protocol checkers, formal verification, emulation, or hardware acceleration methodologies.
• Experience with Python, Perl, or Tcl for verification automation and regression infrastructure.
• Understanding of AI or data-center system architectures, including accelerator, memory, and fabric connectivity.

Culture & Benefits

• Collaboration with architecture, RTL, firmware, design, and post-silicon teams.
• Opportunity to contribute to connectivity products supporting AI accelerators, memory, and compute resources at scale.
• Potential eligibility for discretionary bonuses, incentives, and benefits.
• Commitment to an inclusive workplace that welcomes diverse backgrounds and experiences.