IP Design Verification Engineer (SystemVerilog/UVM)

Location: Hybrid role based at hirify.global sites in Hillsboro, Oregon, or Folsom, California, United States

Annual salary: $105,650–$200,340 USD

Company

hirify.global develops semiconductor technologies and next-generation silicon manufacturing platforms.

What you will do

• Build and maintain scalable, reusable UVM-based testbenches and test cases for mixed-signal CMOS designs at block, subsystem, and SoC levels.
• Define verification strategies and drive coverage closure across multiple projects.
• Develop RTL designs and integrate logic components and IP into SoC architectures.
• Implement power-aware verification methodologies and apply SystemVerilog Assertions.
• Debug pre-silicon failures, perform root-cause analysis, and drive corrective actions to closure.
• Collaborate with architecture, physical design, IP provider, and post-silicon teams while maintaining test plans and leading technical reviews.

Requirements

• Master's degree in Electrical Engineering, Computer Engineering, or a STEM-related field with at least 1 year of relevant experience, or a bachelor's degree with at least 3 years of relevant experience.
• Experience with pre-silicon logic validation using SystemVerilog and UVM.
• Experience with digital design using Verilog and/or SystemVerilog.
• Hands-on experience designing reusable and scalable UVM testbenches and executing end-to-end validation strategies.
• Experience with SystemVerilog Assertions, coverage-driven verification, and validation closure across multiple projects.
• Proficiency in Python, Perl, or TCL for design and verification automation.

Nice to have

• Experience verifying mixed-signal IP such as PLL, DDR, or SerDes.
• Experience with UPF specification and power-aware verification.
• Experience with synthesizable Verilog/SystemVerilog, simulation tools, and timing or power convergence methodologies.
• Experience applying AI/ML techniques to verification automation and efficiency.

Culture & Benefits

• Hybrid work model combining on-site work at an assigned hirify.global site with off-site work.
• Competitive pay with stock bonuses.
• Health, retirement, and vacation benefits.
• Cross-functional collaboration across design, architecture, physical design, and post-silicon teams.