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3 дня назад

Principal Verification Engineer (ASIC)

185 000 - 230 000$
Формат работы
onsite
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

Текст:
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TL;DR
Principal Verification Engineer (ASIC): Leading functional verification of advanced ASICs and SoCs for server and networking applications with an accent on SystemVerilog/UVM, constrained-random testing, emulation, and coverage closure. Focus on developing verification strategies, debugging complex switching architectures, and closing functional coverage gaps across the full verification lifecycle.

Location: San Jose, California, United States

Salary: $185,000–$230,000 per year, depending on experience, level, and business need. Discretionary bonuses, incentives, and benefits may also be available.

Company

hirify.global provides rack-scale AI infrastructure through connectivity solutions based on CXL, Ethernet, NVLink, PCIe, UALink, and its COSMOS software suite.

What you will do

  • Lead functional verification for advanced ASICs, including planning, test development, execution, and coverage analysis.
  • Develop and execute test plans with software and system validation teams on emulation platforms.
  • Apply directed and constrained-random verification techniques using SystemVerilog, UVM, and related tools.
  • Debug test failures, analyze coverage results, and close functional coverage gaps.
  • Collaborate with RTL designers to troubleshoot and resolve design issues.
  • Drive verification strategy and methodology for SoCs used in server and networking applications.

Requirements

  • Bachelor’s degree in Electrical Engineering; a Master’s degree is preferred.
  • 8+ years of SoC verification experience, particularly in server and networking applications.
  • Expertise in SystemVerilog and UVM with experience across the full verification lifecycle.
  • Experience with industry-standard simulators, version control, regression systems, test sequences, stimulus generation, and verification-hole identification.
  • Strong debugging and coverage analysis skills.
  • Experience verifying switching architectures, including packet processing and forwarding engines.

Nice to have

  • Experience with third-party Verification IP for PCIe, Ethernet, or InfiniBand.
  • Background in Network-on-Chip architectures for smart NICs and AI accelerators.
  • Knowledge of Ethernet or PCIe switching and central buffer architectures.
  • Experience with emulation platforms and hardware-software co-verification.

Culture & Benefits

  • Work alongside hyperscalers and ecosystem partners on AI infrastructure connectivity solutions.
  • Collaborative environment involving software, system validation, and RTL design teams.
  • Discretionary bonus, incentives, and benefits may be available.
  • Applications are encouraged from people with diverse backgrounds and experiences.

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