Principal RTL Design Engineer (Verilog/SystemVerilog)

Location: Burnaby, Canada

Annual base salary: $86,000–$186,000 USD

Company

hirify.global develops semiconductor products and mixed-signal integrated circuits for connectivity, embedded, and wireline applications.

What you will do

• Participate in the full ASIC design cycle, from RTL design and verification through backend implementation, silicon bring-up, and debugging.
• Design RTL with Verilog and SystemVerilog, integrate IP blocks, and implement clock/reset, JTAG, DFT, SRAM, and related supporting logic.
• Run CDC analysis, lint checks, power simulations, trial synthesis, and timing-closure activities with backend engineering.
• Collaborate with verification, firmware, product engineering, architecture, and cross-functional teams to create test plans, debug issues, and validate designs.
• Develop C-based drivers for DDR and Flash PHYs, support simulation-based validation, and provide laboratory silicon bring-up support.
• Produce design, verification, test, and characterization documentation.

Requirements

• Bachelor’s, Master’s, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
• 2–10 years of ASIC development experience.
• Strong RTL design and verification experience with Verilog, SystemVerilog, or VHDL.
• Hands-on debugging experience with oscilloscopes, logic analyzers, or similar laboratory equipment.
• Experience with C/C++ and scripting or automation using Python, Perl, TCL, or Shell.
• Strong problem-solving, independent working, and collaboration skills.

Nice to have

• Knowledge of DDR and Flash controllers, PHYs, or memory systems.

Culture & Benefits

• Full-time employment within a large global technology organization.
• Health benefits begin on the first day.
• Retirement savings plans and an employee stock purchase program with a six-month look-back feature.
• Compensation includes base pay, restricted stock units, and quarterly bonuses.
• Expected travel is 0%–25%.