Physical Design Engineer

Location: US Headquarters

Base salary: $140,000–$156,000 per year

Company

hirify.global develops low-power AI vision processors for edge applications that extract data from high-resolution video streams.

What you will do

• Implement and verify SoC physical design from netlist through GDSII at block and full-chip levels.
• Perform floor-planning, automated place and route, engineering change order implementation, and physical layout verification.
• Conduct static timing, signal integrity, and EM/IR analyses, including multi-mode multi-corner analysis.
• Analyze and resolve critical timing issues to support tape-out-quality designs.
• Apply hierarchical physical design strategies and methodologies for advanced nanometer technologies.

Requirements

• BS or MS in Electrical Engineering, Computer Science, or equivalent experience.
• 3–5+ years of relevant physical design experience.
• Strong understanding of VLSI digital design, layout, timing closure, circuit design, device delays, and gate-level timing.
• Experience with Cadence Innovus, Quantus, Tempus, Synopsys Fusion Compiler, ICC2, StarRC, PrimeTime, or Mentor Calibre.
• Proficient programming and scripting skills in Perl, Python, TCL, C-shell, and make; familiarity with Verilog or VHDL.
• Ability to work collaboratively with strong verbal and written communication skills.

Nice to have

• Experience with Cadence Innovus, Genus, or Conformal and Synopsys PrimeTime or StarRC.
• Hands-on experience delivering tape-out-quality GDSII with silicon success in sub-10 nm technologies.

Culture & Benefits

• Opportunity to convert to a full-time regular position.
• New-hire RSU grants and eligibility for annual RSU grants.
• Competitive benefits package.