Principal Physical Design Engineer, Methodology (EDA)

Location: Fully onsite in San Jose, California, United States

Base salary: $185,000–$240,000 per year, depending on experience, level, and business need. Discretionary bonus, incentives, and benefits may be available.

Company

hirify.global provides rack-scale AI infrastructure through semiconductor-based connectivity solutions and the COSMOS software suite, integrating technologies such as CXL, Ethernet, NVLink, PCIe, and UALink.

What you will do

• Define, develop, and maintain reusable physical design flows covering synthesis, place-and-route, extraction, static timing analysis, and EMIR.
• Own the end-to-end RTL-to-GDSII infrastructure across Cadence and Synopsys toolchains.
• Evaluate tools, foundry enablement kits, and flow enhancements to improve PPA and schedule predictability.
• Build automation for large-scale multi-corner/multi-mode STA and EMIR runs, including partitioning and resource optimization.
• Develop QoR tracking and optimization frameworks across multiple programs.
• Establish standards, quality checks, documentation, and training while supporting physical design engineers with flow and methodology issues.

Requirements

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related field; a master’s degree is preferred.
• 8+ years of experience in physical design methodology, CAD, or flow development for complex SoCs at advanced nodes of 7nm and below.
• Strong knowledge of synthesis, place-and-route, extraction, STA, and equivalence checking flows.
• Experience with Cadence Innovus, Tempus, Voltus, and Pegasus, as well as Synopsys Fusion Compiler, PrimeTime, StarRC, and ICC2.
• Expert scripting skills in Python, Tcl, and/or Perl, plus experience with multi-corner/multi-mode analysis infrastructure.
• Understanding of foundry design rules, technology files, enablement kit integration, and independent prioritization.

Nice to have

• Knowledge of agentic AI solutions for EDA automation.
• Experience integrating CI/CD into physical design flows.
• Familiarity with compute farm management and job scheduling optimization.
• Knowledge of advanced packaging or multi-die integration flows.

Culture & Benefits

• Discretionary bonus and incentive eligibility may be available.
• Benefits may be provided with the role.
• A diverse and inclusive workplace encourages applications from people with varied backgrounds and experiences.