Physical Design Implementation and STA Lead

Location: San Jose, California, United States

Salary: $149,100–$215,000 USD annually for the Bay Area California region, plus incentive opportunities.

Company

hirify.global is an independent pure-play FPGA solutions provider developing programmable technologies for AI, cloud, networking, and edge markets.

What you will do

• Lead block-level physical implementation from synthesis and floorplanning through place-and-route, clock tree synthesis, optimization, and ECO closure.
• Support SoC-level implementation, floorplan partitioning, integration strategies, and convergence across timing, power, congestion, and routability objectives.
• Lead static timing analysis and timing closure across multi-mode multi-corner process, voltage, and temperature conditions using Synopsys PrimeTime or equivalent tools.
• Resolve setup, hold, recovery, removal, signal-integrity, crosstalk, and clock-related timing violations while driving timing-driven ECO implementation.
• Execute signoff activities including IR drop, electromigration, DRC, LVS, antenna, and physical verification.
• Develop Tcl and Python automation, evaluate ML/AI-assisted implementation technologies, and provide technical guidance to physical design engineers.

Requirements

• Bachelor's degree in Electrical Engineering, Computer Engineering, or a related technical discipline.
• 7+ years of experience in physical design, physical implementation, or SoC backend development for advanced semiconductor products.
• 5+ years of block-level physical implementation experience, including synthesis, floorplanning, place-and-route, CTS, optimization, and ECO closure.
• 3+ years of static timing analysis experience with Synopsys PrimeTime or an equivalent STA tool, including MMMC analysis.
• Applicants must be eligible for any required U.S. export authorizations.

Nice to have

• Master's degree in Electrical Engineering, Computer Engineering, or a related technical discipline.
• 10+ years of physical design and STA experience for advanced semiconductor products.
• Experience with 7nm, 5nm, or smaller process technologies, SoC physical implementation, and top-level timing closure.
• Experience implementing high-speed interfaces such as PCIe, Ethernet, SerDes, DDR, LPDDR, or HBM.

Culture & Benefits

• Regular full-time employment with Shift 1 working hours in the United States.
• Incentive opportunities based on individual and company performance.
• Technical collaboration with RTL, architecture, DFT, CAD, packaging, library, and signoff teams.