9 часов назад
Physical Design/CAD Engineer (ASIC)
135 000 - 165 000$
Вакансия из Hirify Global, списка международных tech-компанийДля мэтча и отклика нужен Plus
Мэтч & Сопровод
Для мэтча с этой вакансией нужен Plus
Описание вакансии
Текст:
TL;DR
Physical Design/CAD Engineer (ASIC): Building and improving physical design flows for connectivity ASICs with an accent on RTL-to-GDS ownership, synthesis, place-and-route, timing closure, and signoff. Focus on solving complex SoC and subsystem convergence challenges, validating EM-IR and DRC/LVS results, and developing high-performance EDA methodologies.
Location: San Jose, California, United States; fully on-site and in-person
Salary: $135,000–$165,000 USD annually for Senior Level; $160,000–$195,000 USD annually for Staff Level
Company
provides rack-scale AI infrastructure through semiconductor-based connectivity solutions and software for hyperscalers, server manufacturers, and network OEMs.
What you will do
- Build and support physical design flows for industry-leading EDA tools.
- Drive synthesis, place-and-route, extraction, timing, EM-IR, DRC, LVS, and other signoff activities for complex SoCs and subsystems.
- Architect flow improvements and enhance methodologies for high-performance designs.
- Define physical design requirements with cross-functional teams to achieve optimal power, performance, and area.
- Own small block partitions and closure activities, including PnR, STA, DRC, and LVS.
- Partner with design, implementation, and verification teams to drive block and full-chip convergence.
Requirements
- Bachelor’s degree in Electrical Engineering or Computer Science; a Master’s degree is preferred.
- 2–10 years of experience in PnR and signoff for complex SoCs in server, storage, or networking applications.
- Expertise in PnR, extraction, timing closure, EM-IR, Formality, and DRC/LVS at block and full-chip levels.
- Strong knowledge of synthesis, place-and-route, extraction, and equivalence-checking flows in advanced nodes of 7nm or below.
- Proficiency with Cadence and/or Synopsys physical design and STA toolchains.
- Strong scripting skills in Tcl, Python, and Perl, with the ability to work independently and prioritize effectively.
Nice to have
- Knowledge of agentic AI solutions.
- Experience working with EDA/IP vendors on RTL and hard-macro integration.
- Familiarity with high-speed SERDES and Ethernet PHY timing challenges.
- Knowledge of ECO methodologies, DFT tools, and test coverage analysis.
Culture & Benefits
- Work alongside design, implementation, verification, and vendor teams.
- Contribute to connectivity ASICs used by leading cloud service providers and server and network OEMs.
- Work in an environment that values creativity, innovation, and diverse perspectives.
- Base salary is determined by experience and compensation levels for similar positions.
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