Principal Physical Design Engineer

Location: San Jose, California, United States

Salary: $185,000–$230,000 per year, depending on experience, level, and business need. The role may also include discretionary bonuses, incentives, and benefits.

Company

hirify.global provides rack-scale AI infrastructure through semiconductor-based connectivity solutions and its COSMOS software suite, integrating CXL, Ethernet, NVLink, PCIe, and UALink technologies.

What you will do

• Own the end-to-end RTL2GDS flow across advanced process nodes, including synthesis, floorplanning, placement, clock-tree synthesis, routing, and signoff.
• Drive block- and chip-level place-and-route strategy, congestion resolution, routing convergence, and clocking topology for high-frequency, high-density designs.
• Lead tapeout execution, including ECO closure, GDS handoff, and post-tapeout support through fabrication.
• Drive multi-mode multi-corner STA closure, low-power implementation, IR/EM analysis, and physical verification through clean signoff.
• Partner with RTL, DFT, analog/mixed-signal, package, and CAD teams on floorplanning, clocking, and power-delivery strategies.
• Establish physical design methodology, develop automation scripts and flows, mentor engineers, and represent Physical Design in program-level technical decisions.

Requirements

• Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field.
• 8+ years of physical design experience with multiple tapeouts on advanced process nodes of 7nm or below.
• Deep expertise in synthesis, place and route, clock-tree synthesis, and timing closure using Synopsys Fusion Compiler or ICC2, Cadence Innovus, and PrimeTime.
• Strong knowledge of low-power design techniques, including multi-Vt, power gating, DVFS, and UPF.
• Proficiency in Tcl or Python scripting for flow automation.
• Production experience delivering high-frequency, high-complexity SoC blocks or full-chip implementations.

Nice to have

• MS in Electrical Engineering or Computer Engineering.
• Experience with SerDes-heavy designs, PCIe Gen 6/7, or UALink/UCIe connectivity SoCs.
• Experience with hierarchical implementation and full-chip integration of designs exceeding 500M gates.
• Familiarity with EMIR, thermal, and package co-design considerations.
• Experience mentoring senior engineers and driving methodology adoption across teams.

Culture & Benefits

• Work on connectivity silicon powering rack-scale AI infrastructure.
• Collaborate across RTL, DFT, analog, package, and CAD disciplines.
• Participate in a diverse and inclusive environment that values varied ideas, backgrounds, and experiences.
• Potential eligibility for discretionary bonuses, incentives, and benefits.