Program Management - Principal TPM – Packaging, SI/PI & System Integration (Advanced Packaging)

Location: On-site in the Bay Area, United States

Company

hirify.global is an early-stage chiplet technology startup developing high-performance, power-efficient chip-to-chip communication and chiplet-based systems.

What you will do

• Own schedules, milestones, risks, and execution for advanced packaging, SI/PI, and system integration programs from feasibility through qualification and production ramp.
• Coordinate packaging workstreams covering 2.5D/3D IC integration, chiplet interposers and substrates, bump/RDL planning, and co-packaged optics.
• Manage multiple concurrent programs, assess downstream impacts, resolve scope conflicts, and reprioritize commitments.
• Align package/SI-PI engineering, physical design, DFT, analog, PCB, platform, silicon bring-up, and optical product development teams.
• Manage OSAT partners, substrate vendors, foundries, customers, and technology partners through packaging deliverables and integration milestones.
• Lead program reviews, reporting, budget allocation, resource planning, risk mitigation, and process improvement.

Requirements

• Bachelor’s or Master’s degree in Electrical Engineering, Mechanical Engineering, Materials Science, or a related field.
• 15+ years of semiconductor program management experience with substantial advanced packaging and/or SI/PI program execution.
• Hands-on experience with advanced packaging such as 2.5D/3D integration, flip-chip, interposers, substrate/RDL, CoWoS, InFO, or EMIB.
• Deep understanding of SI/PI, package, system design flows, packaging lifecycle, assembly processes, reliability qualification, and DFM/DFR.
• Experience managing OSAT, substrate vendor, and foundry relationships through qualification and production.
• Strong leadership, problem-solving, decision-making, communication, and project management skills, including Agile or Waterfall methodologies.

Nice to have

• Experience with co-packaged optics or advanced heterogeneous integration.
• Knowledge of HPC, AI/ML accelerator packaging, or networking ASIC packaging.
• Familiarity with package- or system-level signal/power integrity simulation and analysis.
• Experience creating program dashboards, RAID logs, or portfolio-level reporting.

Culture & Benefits

• Work on chiplet interconnect technology for high-performance and power-efficient systems.
• High-visibility role with direct exposure to founders and executive leadership.
• Competitive salary, meaningful equity, and comprehensive benefits.
• Collaborative, first-principles work environment with significant ownership and influence.