Program Management - Principal / Sr. Principal Technical Program Manager – IP, ASIC & Chiplet Platforms

Location: On-site in the Bay Area, United States

Company

hirify.global develops NuLink™ die-to-die PHY IP and NuGear™ chiplet solutions for high-performance AI, HPC, and networking silicon systems using UCIe and proprietary interconnect technology.

What you will do

• Own end-to-end execution of IP, ASIC, and platform programs from architecture and IP definition through design, verification, silicon bring-up, and production readiness.
• Build integrated schedules across design, verification, DFT, physical design, packaging, software, and platform engineering, and drive critical paths to closure.
• Coordinate digital, verification, DFT, physical design, analog/mixed-signal, packaging, PCB, firmware, software, and silicon bring-up teams.
• Manage external IP vendors, OSAT and packaging partners, customer deliverables, and technical integration.
• Lead milestone planning, risk registers, budget and resource allocation, technical reviews, decision-making, and executive reporting.
• Improve program management processes, tooling, documentation, and reporting as the organization scales.

Requirements

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field, or equivalent practical experience.
• 15+ years of semiconductor program management experience, including pre-silicon and post-silicon execution across at least two complete IP or ASIC programs.
• Experience leading complex, multidisciplinary semiconductor programs from architecture through volume production and managing multiple concurrent programs.
• Deep knowledge of the silicon development lifecycle, including front-end and back-end design, design verification, DFT, packaging, PCB/platform design, and silicon bring-up.
• Experience managing external IP vendors and customer engagements, with strong schedule, risk, budget, communication, and cross-functional leadership skills.
• Experience with program management tools such as Jira, MS Project, Smartsheet, or Confluence and Agile, Waterfall, or hybrid methodologies.

Nice to have

• Experience with chiplet interconnect, UCIe, die-to-die PHY, or advanced 2.5D/3D packaging such as CoWoS or InFO.
• Background in networking ASICs, mixed-signal PHY SoCs, high-performance computing, or AI/ML accelerator silicon.
• Working knowledge of firmware and software bring-up for silicon validation.
• PMP, PgMP, or equivalent program management certification.

Culture & Benefits

• Opportunity to shape program management at a company defining a new semiconductor industry segment.
• High-visibility partnership with founding and technical leadership.
• Competitive salary, meaningful equity, and comprehensive health benefits.
• Collaborative, first-principles engineering culture focused on solving complex technical problems.