Hardware Technical Program Manager (AI/ML)

Location: San Jose, CA, Pittsburgh, PA, or Austin, TX

Salary: $200,000–$240,000 per year, plus bonus and equity.

Company

hirify.global develops energy-efficient general-purpose processors for continuous AI/ML computing in IoT devices and other edge applications.

What you will do

• Own silicon programs from architecture freeze through RTL, verification, physical implementation, tapeout, silicon bring-up, and production release.
• Build and maintain execution schedules, critical paths, dependencies, status reporting, and decision records.
• Coordinate architecture, RTL, DV/emulation, DFT, physical design, IP, package, firmware, software, and supply-chain handoffs.
• Drive tapeout readiness and closure of timing, power, IR/EM, DRC/LVS, DFT coverage, ECO, and GDS handoff requirements.
• Manage silicon arrival, ATE/loadboard readiness, lab scheduling, bug triage, and ECO or respin decisions.
• Coordinate foundry, OSAT, IP, and EDA partners while tracking resources, budgets, escalations, and executive decisions.

Requirements

• B.S. in Electrical or Computer Engineering, Computer Science, or an equivalent field.
• 7+ years of semiconductor, hardware engineering, or program management experience, including at least two complete SoC/ASIC programs through tapeout and silicon bring-up.
• Working fluency in RTL, functional verification, coverage closure, DFT, synthesis, PnR, STA, physical signoff, GDSII handoff, and post-silicon validation.
• Experience building bottoms-up schedules, analyzing critical paths, mapping dependencies, and influencing technical stakeholders without direct authority.
• Strong written and verbal communication skills, including communication with principal engineers and executive audiences.
• Hands-on experience with Jira, Confluence, MS Project or Smartsheet, plus familiarity with Synopsys, Cadence, and Siemens EDA tools.

Nice to have

• Prior hands-on engineering experience in design, DV, or physical design.
• Experience with advanced or FinFET nodes, direct foundry engagement, and TSMC.
• Experience with AI/ML accelerators, dataflow or novel compute architectures, emulation or FPGA prototyping, and pre-silicon software enablement.
• Exposure to package and board co-design, OSAT coordination, EVK/reference board programs, and customer or FAE enablement.
• Familiarity with automotive, industrial, or security quality and compliance frameworks.

Culture & Benefits

• 401(k) match and company-paid benefits.
• Equity program and bonus opportunity.
• Paid parental leave.
• Flexible work practices and support for personal and professional development.