Sr. Principal Program Manager, ASIC Post-Silicon Engineering

Location: San Jose, California, United States

Salary: $205,000–$250,000 per year, depending on experience, level, and business need. The role may also include discretionary bonus, incentives, and benefits.

Company

Provides rack-scale AI infrastructure through semiconductor-based connectivity solutions and software for hyperscalers and ecosystem partners, integrating CXL, Ethernet, NVLink, PCIe, and UALink technologies.

What you will do

• Own integrated post-silicon program plans from silicon power-on through bring-up, validation, qualification, customer sampling, and release to manufacturing.
• Coordinate execution across silicon, firmware, software, platform, compliance, production test, manufacturing, quality, operations, and customer-facing teams.
• Drive validation readiness for high-speed connectivity products, including plan coverage, test content, platform availability, milestone tracking, and issue triage.
• Manage schedules, budgets, resources, dependencies, risks, phase-gate criteria, readiness checkpoints, dashboards, and executive decision forums.
• Lead customer sampling readiness, including sample allocation, release notes, known issues, errata, reference platforms, and validation summaries.
• Drive manufacturing readiness, production ramp execution, ATE readiness, characterization, yield learning, failure analysis, reliability qualification, waivers, and production-release approvals.

Requirements

• 10+ years of experience in semiconductor engineering, post-silicon validation, system validation, silicon bring-up, product engineering, applications engineering, FAE, or technically focused program management.
• Experience leading post-silicon execution for complex ASIC, SoC, FPGA, SerDes, Ethernet, PCIe, CXL, networking, AI infrastructure, cloud, data center, or high-performance computing products.
• Demonstrated experience managing products from first silicon through validation, customer sampling, qualification, release to manufacturing, and manufacturing readiness.
• Deep understanding of silicon validation flows, including bring-up, debug, characterization, interoperability, compliance, regression execution, and issue triage.
• Experience managing firmware development cycles and using Jira, Confluence, dashboards, and issue-tracking systems.
• Strong technical knowledge of high-speed SerDes, Ethernet, PCIe, CXL, NVMe, AI server or data center platforms, signal integrity, link training, protocol compliance, firmware/hardware/software interaction, or board- and system-level debug.

Culture & Benefits

• Work involves collaboration with hyperscalers and ecosystem partners on AI infrastructure products.
• Cross-functional environment spanning engineering, product, operations, quality, manufacturing, and customer-facing organizations.
• Compensation may include discretionary bonus, incentives, and benefits.
• Inclusive workplace that encourages applications from people with diverse backgrounds and experiences.