PD - Sr Staff - Physical Verification Lead | Signoff & DRC

Location: Bay Area; on-site

Company

hirify.global develops chiplet-based products requiring advanced-node silicon and package-level physical verification.

What you will do

• Own end-to-end physical verification signoff from block level through chip top, resolving DRC, LVS, ERC, antenna, and DFM violations before tapeout.
• Define hierarchical and distributed DRC methodologies across multiple abstraction levels and advanced process nodes.
• Lead bump planning and package-level DRC for flip-chip, 2.5D, and 3D chiplet assemblies, including bump arrays, UBM, RDL, keep-out zones, and passivation openings.
• Coordinate die, package, substrate, interposer, physical design, and foundry teams on co-design constraints, EM limits, and IR-drop correlation.
• Develop and maintain Calibre SVRF/TVF and IC Validator runsets, including PDK mappings, derived layers, and rule-deck versioning.
• Build PV automation and reporting infrastructure with Python, Perl, and Tcl, and present waiver and signoff readiness updates at tapeout reviews.

Requirements

• 15+ years of ASIC physical verification experience and a track record of leading advanced-node tapeouts.
• Deep expertise with at least two major foundries, including Intel Foundry, TSMC, Samsung, or GlobalFoundries.
• Experience spanning 28nm through 2nm and strong understanding of evolving DRC rule complexity.
• Expertise in bump planning, package-level DRC, advanced packaging co-design, and die-to-package database integration.
• Strong knowledge of DFM, critical-area analysis, CMP density, RDL reliability, lithography-aware design, and 2.5D/3D chiplet integration.
• Excellent communication and cross-functional collaboration skills with design, package, and foundry teams.

Culture & Benefits

• Work directly with physical design, package engineering, and foundry partners.
• Participate in executive-level tapeout reviews and signoff readiness discussions.
• Work on advanced-node and heterogeneous chiplet integration challenges across multiple foundries.