6 часов назад
Sr. Staff Physical Design Timing Engineer (STA)
217 000 - 267 000$
Мэтч & Сопровод
Для мэтча с этой вакансией нужен Plus
Описание вакансии
Текст:
TL;DR
Sr. Staff Physical Design Timing Engineer (STA) (Silicon Photonics/ASIC): Driving timing constraints development, static timing analysis, and timing closure for leading-edge silicon photonics chips with an accent on multi-mode multi-corner analysis, signoff methodology, and physical design flows. Focus on automating timing ECO generation with Tempus/PrimeTime, balancing power, performance, and area, and completing full-chip timing signoff through tapeout.
Location: Boston, MA, United States; flexible hybrid workplace model
Salary: $217,000–$267,000 USD annually, plus equity and other rewards.
Company
develops photonics-based interconnect and AI data center infrastructure, including 3D-stacked photonics engines for large-scale AI and HPC workloads.
What you will do
- Drive static timing analysis signoff for silicon photonics chips across multiple technology nodes.
- Develop timing constraints and incorporate signoff corners, margins, and derates into timing analysis flows.
- Collaborate with architecture, RTL, DFT, and methodology teams on timing modes, constraints, synthesis, place-and-route, and chip signoff flows.
- Analyze power, performance, and area tradeoffs and integrate them into chip implementation flows.
- Run full-chip STA and project timing summaries across multiple scenarios.
- Automate timing ECO generation with Tempus or PrimeTime and document implementation best practices.
Requirements
- Bachelor’s degree in Electrical Engineering or Computer Engineering.
- 12 years of physical design experience, including at least 5 years of hands-on ASIC STA, timing constraints development, and timing closure.
- Experience with Cadence or Synopsys tools, on-chip variation derates, multi-mode multi-corner constraints, and clock tree building strategies.
- Proficiency in scripting with TCL and Python, Perl, or Shell.
- Strong problem-solving, technical analysis, collaboration, and communication skills.
- Capacity to comply with federally mandated U.S. export control requirements.
Nice to have
- Master’s degree in Electrical Engineering or Computer Engineering.
- At least 8 years of hands-on ASIC STA and timing constraints development and timing closure experience with Cadence or Synopsys tools.
Culture & Benefits
- Medical, dental, and vision coverage.
- Retirement savings matching, life insurance, and disability coverage.
- Vacation, sick leave, public holidays, and paid family leave.
- Training and development opportunities and commuter benefits.
- Equity grants for full-time employees.
Будьте осторожны: если работодатель просит войти в их систему, используя iCloud/Google, прислать код/пароль, запустить код/ПО, не делайте этого - это мошенники. Обязательно жмите "Пожаловаться" или пишите в поддержку. Подробнее в гайде →