Principal IP Signoff & Methodology Engineer (Semiconductor)

Location: San Jose, California, United States

Salary: $175,000–$230,000 USD per year

Company

hirify.global provides rack-scale AI infrastructure through semiconductor-based connectivity solutions and software for hyperscalers and ecosystem partners.

What you will do

• Own the completeness, consistency, configuration management, and release readiness of internal and external IP deliverables.
• Review and validate RTL, SDC timing constraints, synthesized netlists, LEF/DEF, floorplan data, documentation, and package-aware views.
• Run, review, and debug digital signoff and physical verification checks, including timing, DRC, LVS, and PERC.
• Drive root-cause analysis and closure of digital, physical, analog, and mixed-signal signoff issues with design, layout, CAD, packaging, and integration teams.
• Track signoff metrics, release readiness, and risk items across IP and top-level integration activities.
• Improve signoff flows, checklists, automation, naming conventions, and acceptance criteria across multiple IP types.

Requirements

• Strong hands-on experience with RTL, SDC, LEF/DEF, synthesized netlists, timing reports, and physical design artifacts.
• Experience defining signoff metrics, release dashboards, automation, and methodology improvements across multiple programs.
• Strong digital and physical design fundamentals with structured debug and issue-closure skills.
• Ability to collaborate across digital, analog, physical design, CAD, packaging, and SoC integration teams.
• Ability to assess IP readiness for block-level, die, bump, package, and system integration.

Culture & Benefits

• Work focuses on high-performance connectivity and AI infrastructure products.
• Cross-functional collaboration spans IP, digital, analog, physical design, CAD, packaging, and integration disciplines.
• The company encourages applications from candidates with diverse backgrounds and experiences.