Technical Lead Physical Design Engineer (ASIC)

Location: San Jose, California, United States; fully on-site and in-person

Base salary: $135,000–$165,000 USD for Senior Level; $160,000–$195,000 USD for Staff Level.

Company

Provides rack-scale AI infrastructure through semiconductor connectivity solutions integrating CXL, Ethernet, NVLink, PCIe, UALink, and a software suite.

What you will do

• Oversee planning, coordination, and execution of physical design for connectivity ASICs.
• Own blocks from architecture through GDSII and drive multiple complex designs into production.
• Develop and maintain timing constraints, signoff methodologies, and timing closure at block or full-chip level.
• Execute synthesis, place and route, extraction, EM-IR, and formal equivalence verification.
• Collaborate with design, verification, engineering operations, IP vendors, hyperscalers, and ecosystem partners.
• Support customer meetings and prioritize multiple concurrent technical tasks with minimal supervision.

Requirements

• Bachelor’s degree in Electrical Engineering or Computer Engineering; a Master’s degree is preferred.
• At least 5 years of experience supporting or developing complex SoC or silicon products for server, storage, or networking applications.
• Thorough hands-on knowledge of physical design tools and methodologies for technologies at 7nm or less.
• Experience with Cadence and/or Synopsys physical design tools and flows.
• Working knowledge of SystemVerilog or Verilog and scripting with Tcl, Python, or Perl.
• Experience working with RTL and hard-macro IP vendors.

Nice to have

• Knowledge of design for test, ECO methodologies and tools, and LVS/DRC closure.

Culture & Benefits

• On-site collaboration with design, verification, and engineering operations teams.
• Entrepreneurial, open-minded, customer-focused, and proactive working style.
• Inclusive environment encouraging applications from people with diverse backgrounds and experiences.