8 часов назад
Sr. Staff Physical Design Engineer (AI)
217 000 - 267 000$
Мэтч & Сопровод
Для мэтча с этой вакансией нужен Plus
Описание вакансии
Текст:
TL;DR
Sr. Staff Physical Design Engineer (AI): Implementing complex digital blocks and high-performance ASICs at advanced 3nm process nodes with an accent on timing closure, power integrity, physical verification, and photonics system optimization. Focus on full-chip floor planning, clock implementation, STA signoff, ECOs, DRC/LVS closure, and automating physical design flows with TCL and Python.
Location: Boston, Massachusetts, United States; flexible hybrid workplace model
Salary: $217,000–$267,000 USD annually, plus equity and other rewards.
Company
develops photonics-based AI data center infrastructure, including 3D-stacked photonics engines for extreme-scale AI and HPC workloads.
What you will do
- Implement complex digital blocks from synthesis through physical verification using advanced process nodes and industry-standard flows.
- Drive full-chip static timing analysis signoff, review constraints, debug timing reports, and implement functional and timing ECOs.
- Lead power analysis and optimization while balancing area and performance trade-offs.
- Own full-chip floor planning, I/O placement, clock distribution, and customization of functional and test clock implementation.
- Debug and close DRC/LVS issues and collaborate with EDA companies to resolve tool problems.
- Write TCL, Python, or Shell scripts to automate and customize design flows.
Requirements
- Bachelor’s degree in Electrical Engineering or Computer Engineering.
- 12+ years of industry experience as a Physical Design Engineer; a master’s degree with 8 years of experience is preferred.
- Completed block-level or top-level physical design for large ASICs or mixed-signal chips that reached tape-out.
- Thorough knowledge of timing closure and LVS/DRC closure.
- Experience with TCL, Python, or other scripting languages.
- Strong collaboration skills and the ability to work effectively in a fast-paced, changing environment.
Nice to have
- Hands-on experience with Cadence tools.
- Tape-out experience with 3nm designs.
- Willingness to perform manual layouts and learn silicon photonics layout.
- Experience with EM/IR analysis using standard industry signoff tools.
Culture & Benefits
- Work with scientists, engineers, and industry leaders on photonics technology for AI and HPC.
- Medical, dental, and vision coverage.
- Retirement savings matching, life insurance, and short- and long-term disability coverage.
- Vacation, sick leave, public holidays, and paid family leave.
- Training and development, commuter benefits, and equity grants for full-time employees.
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