11 часов назад
Principal SoC RTL Engineer (Verilog/SystemVerilog)
Мэтч & Сопровод
Для мэтча с этой вакансией нужен Plus
Описание вакансии
Текст:
TL;DR
Principal SoC RTL Engineer (Verilog/SystemVerilog): Developing architecture, microarchitecture, and RTL for complex digital SoC modules and IPs on MCU platforms with an accent on pre-tapeout quality, timing, power, and silicon readiness. Focus on integrating third-party IP, debugging with verification and FPGA teams, closing LINT/CDC/RDC issues, and supporting silicon bring-up and validation.
Location: Austin, Texas, United States
Company
develops ultra-low-power semiconductor solutions for wearables, medical devices, IoT products, and AI-powered edge applications.
What you will do
- Own pre-tapeout quality for digital SoC modules on MCU platforms.
- Explore system architecture and develop microarchitecture for next-generation silicon.
- Develop Verilog/SystemVerilog RTL for complex IPs and SoCs.
- Identify, select, and integrate third-party IP.
- Partner with verification and FPGA teams on test planning and debug.
- Collaborate with physical design to meet timing and power targets, run LINT, CDC, and RDC checks, and support silicon bring-up and validation.
Requirements
- Bachelor’s degree in Electronics Engineering, Electrical Engineering, Instrumentation and Control Engineering, or a related field.
- 20 years of professional experience.
- Deep and broad knowledge of current and emerging SoC design technologies.
- Expertise in designing, implementing, and troubleshooting IPs and SoCs.
- Ability to estimate implementation impact, plan and lead technical execution, and guide programs across technical areas.
- Understanding of customer needs and the competitive landscape.
Culture & Benefits
- Cross-functional collaboration across design, research, development, production, marketing, sales, and operations.
- Values-driven environment centered on innovation, collaboration, focus, continuous learning, and execution.
- Opportunity to work on complex semiconductor and energy-efficiency challenges with direct impact on production silicon.
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