Senior RTL Design Engineer - CPU (RISC-V)

Location: Cambridge, England, United Kingdom. Right to work in the United Kingdom is required. Access to export-controlled technology is subject to applicable authorization or export licenses.

Company

hirify.global develops high-performance compute platforms and CPU cores based on the open-source RISC-V architecture for applications including artificial intelligence, machine learning, automotive, data centers, mobile, and consumer devices.

What you will do

• Architect, design, and implement features, performance improvements, and ISA extensions in RISC-V CPU core generators using Chisel.
• Integrate design content into the Chisel/FIRRTL framework and improve automatic generation of documentation, verification testbenches, tests, and packaged software.
• Perform initial sandbox verification and create and execute verification test plans with the design verification team.
• Work with the physical implementation team to optimize designs for frequency, area, and power targets.
• Collaborate with performance modeling engineers on performance exploration and optimization.
• Develop microarchitecture specifications, document designs, and share knowledge through collaborative engineering.

Requirements

• Bachelor’s or master’s degree in computer science, computer engineering, electrical engineering, or a related field, or equivalent experience.
• At least 3 years of design experience, including academic or professional CPU RTL design.
• Proficiency in RTL design with Verilog, SystemVerilog, or VHDL.
• Strong software engineering background, including functional programming, templated metaprogramming, compiler infrastructures, intermediate representations, and test-driven development.
• Attention to detail and commitment to high-quality design.
• Ability to collaborate effectively and contribute to a teamwork-oriented engineering culture.

Nice to have

• Experience with Scala/Chisel, Bluespec, or another language or DSL for configurable hardware.
• Knowledge of RISC-V architecture and CPU processor design areas such as instruction fetch, instruction decode, register renaming, instruction scheduling, vector units, or load-store units.
• Knowledge of verification principles, testbenches, UVM, and coverage.
• Experience with Git/GitHub, Jira, or Confluence.

Culture & Benefits

• Collaborative engineering environment focused on innovation and knowledge sharing.
• Work on CPU cores and hardware IP based on the open-source RISC-V architecture.
• Employment is full time.
• Employment is subject to successful background and reference checks.
• Equal opportunity workplace committed to diversity and inclusion.