5 часов назад
Member of Technical Staff, Hardware, Physical Design Engineer (AI)
200 000 - 420 000$
Мэтч & Сопровод
Для мэтча с этой вакансией нужен Plus
Описание вакансии
Текст:
TL;DR
Member of Technical Staff, Hardware, Physical Design Engineer (AI) (advanced-node silicon): Transforming high-performance architectural concepts into production-ready silicon for a custom AI accelerator with an accent on synthesis, place-and-route, timing closure, and physical verification. Focus on maximizing PPA, resolving signal integrity and power-delivery challenges, co-designing with RTL teams, and automating implementation flows with AI-driven EDA tools.
Location: Austin, Texas or Palo Alto, California, United States
Salary: $200,000–$420,000 USD annually
Company
Develops personal AI products spanning local-inference hardware, bespoke training infrastructure, user interfaces, and deep learning research.
What you will do
- Own the physical implementation flow from RTL synthesis through placement, clock tree synthesis, routing, and tape-out for high-performance hardware blocks.
- Optimize layout topology, cell density, utilization, and power delivery networks to maximize performance, power, and area on advanced process nodes.
- Close timing and electrical constraints by performing static timing analysis and resolving setup, hold, signal integrity, electromigration, and IR-drop issues.
- Run and debug sign-off physical verification, including DRC, LVS, and antenna-rule checks.
- Collaborate with RTL and architecture teams on logic structures, pipeline depth, routing congestion, and implementation closure.
- Develop and integrate AI-driven EDA tools and workflow automation for physical design closure.
Requirements
- Bachelor’s degree in Electrical Engineering or Computer Engineering.
- 5+ years of industry experience with advanced process nodes of 7nm or below.
- Hands-on experience with physical design, timing, and sign-off tools such as Innovus, Fusion Compiler, PrimeTime, and RedHawk.
- Experience with logic synthesis, compiled memory macros, and multi-voltage design using UPF or CPF.
- Strong debugging skills and the ability to balance congestion, timing slack, and power density in highly utilized designs.
- Collaborative experience working with RTL and architecture teams.
Nice to have
- Production tape-outs of high-performance SoCs, CPUs, GPUs, or AI accelerators.
- Physical-layout optimization for systolic arrays, tensor execution units, or HBM interfaces.
- EDA-tool scripting or extension with Tcl, Python, or specialized ML APIs.
Culture & Benefits
- Visa sponsorship is available for the right candidate.
- Relocation support is available as needed.
- Health, dental, and vision benefits.
- Unlimited paid time off.
- Work alongside scientists, engineers, and builders from leading technology companies and AI labs.
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